1. Description
1.1. Hardware and software capabilities
The unit integrated in STM32MP25x and STM32MP23x boards to accelerate the AI processing is the GCNanoUltra31-VIP.
This unit is a combination of GPU and NPU and these two parts are sharing the same parallel processing unit (shaders).
On STM32MP25x:
The NPU part is composed of one AI core that delivers 1.2 TOPS at 800 MHz that can be overdrive to 900 MHz to reach 1.35 TOPS.
On the GPU side, the computing power is 25.6 GFLOPS at 800 MHz when processing 16 bit data.
On STM32MP23x:
The NPU part is composed of one AI core that delivers 0.6 TOPS at 400 MHz.
1.2. Restriction and usage
To access and run an neural network (NN) model on the NPU, you need to use the OpenVX software stack. But, to ease the usage of the NPU software stack, we have developed a stai_mpu unified API that allows you to run an NN model easily. For more information, visit the wiki article on how to use stai_mpu API.
This NPU IP only supports 8-bits NN models quantized with the per-tensor asymmetric quantization scheme. If the quantization scheme is different, like per-channel, the model will run mainly on GPU instead of NPU. You will find in the next section the list of the supported operations on NPU and on GPU with all the information about the data format needed for the execution on the hardware.
The NPU/GPU does not support custom operators coming from other frameworks like TFLite™ or ONNX™, if the model contains such operators they will be removed or conversion to NBG format will fail. However, it is possible to define your own OpenVX operator.
2. Operation support
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Data type abbreviations:
Execution engine abbreviations:
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2.1. Basic operations
This is the list of the basic operations supported by the NPU.
Operation | Type | NPU support | GPU support |
---|---|---|---|
VSI_NN_OP_CONV2D | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_CONV1D | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_CONV3D | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_DECONVOLUTION | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_DECONVOLUTION1D | asym-u8 | ![]() |
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asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_FCL2 | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_GROUPED_CONV1D | asym-u8 | ![]() |
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asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_GROUPED_CONV2D | asym-u8 | ![]() |
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asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_GROUPED_CONV3D | asym-u8 | ![]() |
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asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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2.2. Activation operations
This is the list of the OVXLIB activation operations supported by the NPU.
Operation | Type | NPU support | GPU support |
---|---|---|---|
VSI_NN_OP_ABS | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_ACOSH | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_ATAN | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_ATANH | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_CELU | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_CLIP | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_COS | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_ELU | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_ERF | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_EXP | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_GELU | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_HARD_SIGMOID | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_INVERSE_SIGMOID | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_LEAKY_RELU | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_LINEAR | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_LOG | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_LOG_SOFTMAX | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_MISH | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_NEG | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_PRELU | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_RCP | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_RELU | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_RELUN | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_RSQRT | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SELU | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SIGMOID | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SIGN | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SIN | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SOFTMAX | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SOFTRELU | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SOFTSIGN | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SQRT | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SQUARE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SWISH | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_TANH | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_TAN | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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2.3. Elementwise operations
This is the list of the elementwise operations supported by the NPU.
Operation | Type | NPU support | GPU support |
---|---|---|---|
VSI_NN_OP_ADD | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_ADDN | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_DIVIDE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_FLOORDIV | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_LOGICAL_NOT | bool8 | ![]() |
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VSI_NN_OP_LOGICAL_OPS | bool8 | ![]() |
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VSI_NN_OP_MATRIXMUL | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_MAXIMUM | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_MINIMUM | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_MOD | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_MULTIPLY | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_POW | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_RELATIONAL_OPS | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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bool8 | ![]() |
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VSI_NN_OP_SELECT | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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bool8 | ![]() |
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VSI_NN_OP_SUBTRACT | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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2.4. Normalization operations
This is the list of the normalization operations supported by the NPU.
Operation | Type | NPU support | GPU support |
---|---|---|---|
VSI_NN_OP_BATCH_NORM | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_BATCHNORM_SINGLE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_GROUP_NORM | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_INSTANCE_NORM | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_L2_NORMALIZE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_LAYER_NORM | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_LPNORM | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_LRN2 | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_MOMENTS | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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2.5. Reshape operations
This is the list of the reshape operations supported by the NPU.
Operation | Type | NPU support | GPU support |
---|---|---|---|
VSI_NN_OP_ARGMAX | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_ARGMIN | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_BATCH2SPACE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_CONCAT | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_DEPTH2SPACE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_EXPAND_BROADCAST | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_PAD2 | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_PERMUTE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_REDUCE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_REORG | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_RESHAPE2 | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_REVERSE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SHUFFLECHANNEL | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SLICE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SPACE2BATCH | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SPACE2DEPTH | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SPLIT | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SQUEEZE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_STACK | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_STRIDED_SLICE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_UNSTACK | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_REDUCEL2 | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_RMSNORM | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_L1_LAYER_NORM | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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2.6. RNN operations
This is the list of the recurrent neural network (RNN) operations supported by the NPU.
Operation | Type | NPU support | GPU support |
---|---|---|---|
VSI_NN_OP_CONV2D_LSTM | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_CONV2D_LSTM_CELL | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_GRU | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_GRUCELL | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_LSTM_OVXLIB | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_LSTMUNIT_OVXLIB | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SVDF | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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2.7. Pooling operations
This is the list of the recurrent neural network (RNN) operations supported by the NPU.
Operation | Type | NPU support | GPU support |
---|---|---|---|
VSI_NN_OP_AVG_POOL3D | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_GLOBALLPPOOL | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_LPPOOL | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_MAX_POOL3D | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_MAXPOOLWITHARGMAX | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_MAXUNPOOL | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_POOL | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_POOLWITHARGMAX | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_ROI_POOL | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_UPSAMPLE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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2.8. Miscellaneous operations
This is the list of other operations supported by the NPU.
Operation | Type | NPU support | GPU support |
---|---|---|---|
VSI_NN_OP_BUCKETIZE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_CAST | all types | ![]() |
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VSI_NN_OP_CEIL | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_CONCATSHIFT | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_CUMSUM | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_DATACONVERT | asym-u8 / asym-i8 | ![]() |
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VSI_NN_OP_DROPOUT | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_EMBEDDING_LOOKUP | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_FLOOR | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_GATHER | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_GATHER_ELEMENTS | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_GATHER_ND | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_GRID_SAMPLE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_ONE_HOT | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_PROPOSAL | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_REPEAT | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_RESIZE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_RESIZE_1D | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_RESIZE_3D | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_REVERSESEQUENCE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_ROUND | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SCATTER_ELEMENTS | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SCATTER_ND | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SCATTER_ND_UPDATE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SEQUENCE_MASK | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SIGNAL_FRAME | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_TILE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_UPSAMPLESCALE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_VARIABLE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_CROP_AND_RESIZE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_SHAPE | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_COL2IM | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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VSI_NN_OP_BITCAST | asym-u8 / asym-i8 | ![]() |
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fp32 / fp16 | ![]() |
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2.9. Fuse operation support
This is the list of the operation combinations that the NPU can fuse.
Fuse operation | First operation | ||||
---|---|---|---|---|---|
Second operation | CONV2D | CONV1D | DW_2D | FCL2 | PERMUTE |
ABS | ![]() |
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ACOSH | ![]() |
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ADD | ![]() |
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ATAN | ![]() |
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CELU | ![]() |
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CLIP | ![]() |
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CONV1D | ![]() |
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CONV2D | ![]() |
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DEPTH2SPACE | ![]() |
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DW_2D | ![]() |
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ELU | ![]() |
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ERF | ![]() |
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GELU | ![]() |
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HARD_SIGMOID | ![]() |
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HSWISH | ![]() |
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INVERSE_SIGMOID | ![]() |
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LEAKY_RELU | ![]() |
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LOG | ![]() |
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MAX_POOL | ![]() |
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MISH | ![]() |
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MULTIPLY | ![]() |
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NEG | ![]() |
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PERMUTE | ![]() |
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PRELU | ![]() |
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RCP | ![]() |
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RELU | ![]() |
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RELUN | ![]() |
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RESHAPE | ![]() |
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RSQRT | ![]() |
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SELU | ![]() |
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SIGMOID | ![]() |
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SOFTRELU | ![]() |
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SOFTSIGN | ![]() |
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SPACE2DEPTH | ![]() |
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SQRT | ![]() |
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SQUARE | ![]() |
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SUBTRACT | ![]() |
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SWISH | ![]() |
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TANH | ![]() |
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MAX_POOL + ABS | ![]() |
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MAX_POOL + ACOSH | ![]() |
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MAX_POOL + ADD | ![]() |
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MAX_POOL + ATAN | ![]() |
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MAX_POOL + BATCH_NORM | ![]() |
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MAX_POOL + CELU | ![]() |
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MAX_POOL + CLIP | ![]() |
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MAX_POOL + ELU | ![]() |
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MAX_POOL + ERF | ![]() |
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MAX_POOL + GELU | ![]() |
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MAX_POOL + HARD_SIGMOID | ![]() |
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MAX_POOL + HSWISH | ![]() |
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MAX_POOL + INVERSE_SIGMOID | ![]() |
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MAX_POOL + LEAKY_RELU | ![]() |
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MAX_POOL + MISH | ![]() |
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MAX_POOL + MULTIPLY | ![]() |
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MAX_POOL + NEG | ![]() |
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MAX_POOL + PRELU | ![]() |
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MAX_POOL + RCP | ![]() |
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MAX_POOL + RELU | ![]() |
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MAX_POOL + RELUN | ![]() |
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MAX_POOL + RSQRT | ![]() |
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MAX_POOL + SELU | ![]() |
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MAX_POOL + SIGMOID | ![]() |
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MAX_POOL + SOFTRELU | ![]() |
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MAX_POOL + SOFTSIGN | ![]() |
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MAX_POOL + SQRT | ![]() |
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MAX_POOL + SQUARE | ![]() |
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MAX_POOL + SUBTRACT | ![]() |
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MAX_POOL + SWISH | ![]() |
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MAX_POOL + TANH | ![]() |
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