1. Article purpose[edit | edit source]
The purpose of this article is to explain how to configure the FMC using the device tree mechanism, relying on the bindings documentation, that is the description of the required and optional device-tree properties.
The peripheral can be assigned to different contexts/software components, depending on the final product needs.
Refer to How to assign an internal peripheral to an execution context article for guidelines on this configuration.
2. DT bindings documentation[edit | edit source]
The device tree binding documents are stored either in the given applicable components listed below, or in the Linux kernel repository.
- TF-A BL2, U-Boot, Linux® OS:
- Generic MTD NAND device tree bindings - Documentation/devicetree/bindings/mtd/nand-controller.yaml
- FMC NAND Flash controller device tree bindings - Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml
- FMC external bus interface device tree bindings - Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml .
- OP-TEE:
- FMC external bus interface device tree bindings - documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml .
3. DT configuration[edit | edit source]
This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the Device tree for an explanation of the device tree file organization.
STM32CubeMX can be used to generate the board device tree.
Refer to How to configure the DT using STM32CubeMX for more details.
3.1. DT configuration (STM32 level)[edit | edit source]
The FMC node is located in the device tree file for the software components, supporting the peripheral and listed in the above DT bindings documentation paragraph.
3.2. DT configuration (board level)[edit | edit source]
The objective of this chapter is to explain how to enable and configure the FMC DT nodes for a board.
Peripheral configuration should be done in specific board device tree files (board dts file and pinctrl dtsi file).
3.2.1. DT configuration of FMC resources assignment[edit | edit source]
On STM32MP2 series, FMC is a RIF-aware peripheral and it is possible to assign the different FMC internal controller to different execution contexts.
As all RIF configuration of the platform, FMC RIF register must be configured by the secure OS of the main processor (TDCID). RMC resource assignment is defined in main processor secure OS board device tree file.
In the following example:
- FMC external bus interface (R1) controlling external device number 1 (chip select 1) is assigned to the Cortex-M33 non-secure context
- FMC Nand controller (R5) is assigned to the Cortex-A35 non-secure context
Consequently, the common FMC resources (R0) is assigned to main processor secure OS (CID1 secure context in the case of Cortex-A35 main processor.
&fmc {
st,protreg = <
FMC R0 assigned to main processor secure context
RIFPROT(RIF_FMC_CTRL(0), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
FMC R1 assigned to Cortex-M33 non-secure context
RIFPROT(RIF_FMC_CTRL(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN)
FMC R2, R3 and R4 not assigned and not accessible by any context
RIFPROT(RIF_FMC_CTRL(2), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
RIFPROT(RIF_FMC_CTRL(3), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
RIFPROT(RIF_FMC_CTRL(4), EMPTY_SEMWL, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
FMC R5 assigned to Cortex-A35 non-secure context
RIFPROT(RIF_FMC_CTRL(5), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
>;
};
3.2.2. DT configuration of the external bus interface controller (board level)[edit | edit source]
The FMC external bus interface controller can connect up to four external devices.
&fmc { Comments
pinctrl-names = "default", "sleep"; --> For pinctrl configuration, please refer to Pinctrl device tree configuration
pinctrl-0 = <&fmc2_pins_b>;
pinctrl-1 = <&fmc2_sleep_pins_b>;
status = "okay"; --> Enable the node
ksz8851: ks8851mll@1,0 {
compatible = "micrel,ks8851-mll"; --> Configure the external device
reg = <1 0x0 0x2>, <1 0x2 0x20000>;
interrupt-parent = <&gpioc>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
bank-width = <2>;
st,fmc2-ebi-cs-mux-enable; --> Configure the transactions with the external device
st,fmc2-ebi-cs-transaction-type = <4>;
st,fmc2-ebi-cs-buswidth = <16>;
st,fmc2-ebi-cs-address-setup-ns = <5>;
st,fmc2-ebi-cs-address-hold-ns = <5>;
st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
st,fmc2-ebi-cs-data-setup-ns = <45>;
st,fmc2-ebi-cs-data-hold-ns = <1>;
};
};
3.2.3. DT configuration of the NAND Flash controller (board level)[edit | edit source]
The FMC NAND Flash controller can connect to one SLC NAND Flash memory (with a maximum of 2 dies per package).
&fmc { Comments
pinctrl-names = "default", "sleep"; --> For pinctrl configuration, please refer to Pinctrl device tree configuration
pinctrl-0 = <&fmc2_pins_a>;
pinctrl-1 = <&fmc2_sleep_pins_a>;
status = "okay"; --> Enable the node
nand-controller@4,0 {
status = "okay"; --> Enable the NAND controller node
nand@0 {
reg = <0>; --> Describe the CS line assigned to the NAND chip
nand-on-flash-bbt; --> Store the bad block table on NAND Flash memory
nand-ecc-strength = <8>; --> Number of bits to correct per ECC step
nand-ecc-step-size = <512>; --> Number of data bytes that are covered by a single ECC step
#address-cells = <1>;
#size-cells = <1>;
};
};
};
The supported ECC strength and step size are:
- nand-ecc-strength = <1>, nand-ecc-step-size = <512> (HAMMING)
- nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4)
- nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8).
3.3. DT configuration examples[edit | edit source]
The below example shows how to configure the FMC NAND Flash controller when a SLC 8-bit NAND Flash memory device is connected (ECC requirement: 8 bits / 512 bytes).
&fmc {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&fmc2_pins_a>;
pinctrl-1 = <&fmc2_sleep_pins_a>;
status = "okay";
nand-controller@4,0 {
status = "okay";
nand: nand@0 {
reg = <0>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
...
};
};
};
};
The below example shows how to configure the FMC NAND Flash controller when a SLC 8-bit NAND Flash memory device is connected (ECC requirement: 4 bits / 512 bytes).
&fmc {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&fmc2_pins_a>;
pinctrl-1 = <&fmc2_sleep_pins_a>;
status = "okay";
nand-controller@4,0 {
status = "okay";
nand: nand@0 {
reg = <0>;
nand-on-flash-bbt;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
...
};
};
};
};
4. How to configure the DT using STM32CubeMX[edit | edit source]
The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.
STM32CubeMX may not support all the properties described in DT binding files listed in the above DT bindings documentation paragraph. If so, the tool inserts user sections in the generated device tree. These sections can then be edited to add some properties, and they are preserved from one generation to another. Refer to STM32CubeMX user manual for further information.
5. References[edit | edit source]
Refer to the following links for additional information:
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 