- Last edited 3 months ago ago
How to change the CPU frequency
Contents
1 Purpose[edit]
This article explains how to change the CPU operating point (also known as OPP). An operating point corresponds to the frequency of the processor and the voltage that needs to be supplied to sustain it.
It also shows how it is possible to define multiple operating points, allowing the system to jump among them at run time: this is the dynamic voltage and frequency scaling (DVFS). Some cautions are given at the end of the article, to help the user in its DVFS deployment.
2 Hardware side[edit]
On STM32MP1 series products, the Cortex-A7 core:
- can be clocked by PLL1 from the RCC internal peripheral: the PLL1P output frequency can be directly propagated to the core, or it can go through an intermediate MPUDIV divider
- is supplied with
- VDDCPU voltage on STM32MP13x lines
- VDDCORE voltage on STM32MP15x lines
- VDDCPU voltage on STM32MP13x lines
The part number tells the device maximum supported frequency, up to 1 GHz for the STM32MP13 or up to 800 MHz for the STM32MP15, with associated usage conditions. Otherwise, the frequency must be kept below 650 MHz.
3 Software side[edit]
3.1 Boot time[edit]
In OpenSTLinux distribution, TF-A BL2 sets the CPU frequency to 650 MHz, that is the maximum frequency sustainable with the nominal voltage.
Notice that the processor must receive the nominal voltage during TF-A BL2 execution, whether configuring the STPMIC1 from TF-A BL2 itself or getting it from a discrete power supply, depending on the hardware board configuration.
3.1.1 On STM32MP13x lines [edit]
3.1.1.1 VDDCPU voltage configuration[edit]
The example below sets STPMIC1 BUCK1 minimal voltage to 1.25 V, allowing to provide the expected nominal voltage on VDDCPU for the CPU:
vddcpu: buck1 {
regulator-name = "vddcpu";
regulator-min-microvolt = <1250000>;
...
};
3.1.1.2 CPU frequency configuration[edit]
TF-A is using an algorithm to calculate the PLL1 settings in drivers/st/clk/clk-stm32mp13.c .
3.1.2 On STM32MP15x lines [edit]
3.1.2.1 VDDCORE voltage configuration[edit]
The example below sets STPMIC1 BUCK1 minimal voltage to 1.2 V, allowing to provide the expected nominal voltage on VDDCORE for the CPU:
vddcore: buck1 {
regulator-name = "vddcore";
regulator-min-microvolt = <1200000>;
...
};
3.1.2.2 CPU frequency configuration[edit]
TF-A is using an algorithm to calculate the PLL1 settings in drivers/st/clk/stm32mp1_clk.c .
3.2 Runtime[edit]
3.2.1 On STM32MP13x lines [edit]
3.2.1.1 Overview[edit]
By default, in OpenSTLinux distribution, the OP-TEE "soc extension" device tree file defines an OPP table that contains one or several frequency / voltage pair(s).
3.2.1.2 OPP table[edit]
At runtime, Linux will automatically request to OP-TEE SCMI interface to switch between the available operating points according to the CPU load and thanks to Linux cpufreq framework, configured with "ondemand" governor policy (see Documentation/admin-guide/pm/cpufreq.rst ). This feature is called dynamic voltage and frequency scaling (DVFS).
In core/arch/arm/dts/stm32mp13xd.dtsi , two operating points ([1 GHz ; 1.35 V]; [650 MHz ; 1.25 V]) are defined for a 1 GHz capable part number (opp-supported-hw = <0x2>):
&cpu0_opp_table {
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1350000>;
opp-supported-hw = <0x2>;
st,opp-default;
};
opp-650000000 {
opp-hz = /bits/ 64 <650000000>;
opp-microvolt = <1250000>;
opp-supported-hw = <0x2>;
};
};
In core/arch/arm/dts/stm32mp13xa.dtsi , one operating point ([650 MHz ; 1.25 V]) is defined for a 650 MHz capable part number (opp-supported-hw = <0x1>):
&cpu0_opp_table {
opp-650000000 {
opp-hz = /bits/ 64 <650000000>;
opp-microvolt = <1250000>;
opp-supported-hw = <0x1>;
st,opp-default;
};
};
The PLL1 configurations needed to reach the above frequencies must be described via the st,clk_opp, st,pll@0 and st,pll_vco property in 'rcc' device tree node on OP-TEE device tree.
For example in core/arch/arm/dts/stm32mp135f-dk.dts :
&rcc {
st,pll_vco {
pll1_vco_2000Mhz: pll1-vco-2000Mhz {
src = <CLK_PLL12_HSE>;
divmn = <1 82>;
frac = <0xAAA>;
};
pll1_vco_1300Mhz: pll1-vco-1300Mhz {
src = <CLK_PLL12_HSE>;
divmn = <2 80>;
frac = <0x800>;
};
...
};
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
compatible = "st,stm32mp1-pll";
reg = <0>;
st,pll = <&pll1_cfg1>;
pll1_cfg1: pll1_cfg1 {
st,pll_vco = <&pll1_vco_1300Mhz>;
st,pll_div_pqr = <0 1 1>;
};
pll1_cfg2: pll1_cfg2 {
st,pll_vco = <&pll1_vco_2000Mhz>;
st,pll_div_pqr = <0 1 1>;
};
};
....
st,clk_opp {
st,ck_mpu {
cfg_1 {
hz = < 1000000000 >;
st,clksrc = < CLK_MPU_PLL1P >;
st,pll = < &pll1_cfg2 >;
};
cfg_2 {
hz = < 650000000 >;
st,clksrc = < CLK_MPU_PLL1P >;
st,pll = < &pll1_cfg1 >;
};
};
};
};
Notes:
- The operating point(s) supported by devices able to run above 650 MHz (and up to 1 GHz) is/are identified by the opp-supported-hw property set to 0x2.
- OP-TEE configure the OPP selected by st,opp-default during the cold boot
- This description is valid for cold boot, but also when coming back from Standby low power mode.
3.2.2 On STM32MP15x lines [edit]
3.2.2.1 Overview[edit]
By default, in OpenSTLinux distribution, the Linux kernel "soc extension" device tree file defines an OPP table that contains one or several frequency / voltage pair(s).
3.2.2.2 OPP table[edit]
At runtime, the Linux kernel will automatically switch between the available operating points according to the CPU load and thanks to Linux cpufreq framework, configured with "ondemand" governor policy (see Documentation/admin-guide/pm/cpufreq.rst ). This feature is called dynamic voltage and frequency scaling (DVFS).
In core/arch/arm/dts/stm32mp15xd.dtsi , two operating points ([800 MHz ; 1.35 V]; [400 MHz ; 1.2 V]) are defined for a 800 MHz capable part number (opp-supported-hw = <0x2>):
&cpu0_opp_table {
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1350000>;
opp-supported-hw = <0x2>;
st,opp-default;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1200000>;
opp-supported-hw = <0x2>;
opp-suspend;
};
};
In core/arch/arm/dts/stm32mp15xa.dtsi , one operating points ([400 MHz ; 1.2 V]) are defined for a 650 MHz capable part number (opp-supported-hw = <0x1>):
&cpu0_opp_table {
opp-650000000 {
opp-hz = /bits/ 64 <650000000>;
opp-microvolt = <1200000>;
opp-supported-hw = <0x1>;
st,opp-default;
};
};
OP-TEE is using an algorithm to calculate the PLL1 settings in core/drivers/clk/clk-stm32mp15.c , pll1_config_from_opp_khz().
Notes:
- The operating point(s) supported by devices able to run above 650 MHz (and up to 800 MHz) is/are identified by the opp-supported-hw property set to 0x2.
- This same OPP table must be present in both the BL32 (OP-TEE) and Linux device tree
- OP-TEE configure the OPP selected by st,opp-default during the cold boot
- This description is valid for cold boot, but also when coming back from Standby low power mode.
- During cold boot, BL32 (OP-TEE computes and saves the PLL1 settings for all operating points available in the device tree in compliance with the hardware capabilities. These saved paramaters are used later to increase the performance of the system-state transitions.
- Selecting OPP frequencies that can be reached with RCC MPUDIV dividor and without configuring again the PLL1 is recommended in order to get the fastest switch time between the OPP.
4 Dynamic voltage and frequency scaling (DVFS) caution[edit]
As stated above, as soon as at least two operating points are defined in the OPP table, Linux kernel will automatically switch between them at runtime thanks to Linux cpufreq framework, configured with "ondemand" governor policy (see Documentation/admin-guide/pm/cpufreq.rst ). It is important to notice that cpufreq framework is only monitoring the CPU load to select the OPP because this can lead to some limitation during use cases where the CPU is not loaded a lot but high reactivity is needed to respect some real time constraints, like interrupt management. If you face some system issue where the CPU reactivity may be the root cause whereas DVFS is enabled, consider doing a trial with "performance" governor (see Documentation/admin-guide/pm/cpufreq.rst ).