- Last edited 4 months ago ago
1 Article purpose
The purpose of this article is to:
- briefly introduce the Arm® Cortex®-A7 core and its main features
- indicate the level of security supported by this processor
2 Peripheral overview
The Arm Cortex-A7 can be instantiated several times into a single cluster:
- The STM32MP13 main processor is a Cortex-A7 cluster embedding a single core.
- The STM32MP15 main processor is a Cortex-A7 cluster embedding one or two core(s), depending on the selected line.
The Cortex-A7 is a 32-bit processor that belongs to ARMv7-VE architecture family. ARMv7-VE corresponds to the ARMv7-A architecture, with virtual extensions. Among a wide range of features, it includes a memory management unit (MMU), a separate L1 cache and a unified L2 cache in order to efficiently support rich operating systems such as Linux, with a high level of performance.
Refer to the STM32MP13 reference manuals or the STM32MP15 reference manuals for the complete list of features.
2.2 Security support
The Cortex-A7 supports a non-secure and a secure modes that define two hardware execution contexts, named Cortex-A7 non-secure and Cortex-A7 secure.
3 Peripheral usage and associated software
All the software components executed by the Cortex-A7, at boot time and at runtime, constitute the OpenSTLinux distribution.
3.1 Boot time
As soon as the STM32MP1 is powered up, the Cortex-A7 starts to execute the ROM code, which is the first stage of the boot chain. It then executes the FSBL TF-A in secure mode before jumping to the SSBL U-Boot in non-secure mode.
The Cortex-A7 runs Linux in non-secure mode and OP-TEE in secure mode. Linux is executed in SMP mode on the dual-core versions, as explained in the above.
3.2.2 Software frameworks
3.2.3 Peripheral configuration
The Cortex-A7 configuration is done by the various components running on it, according to build-time parameters, and also information from the device tree.
3.2.4 Peripheral assignment
The Cortex-A7 is the main processor supporting Cortex-A7 secure and Cortex-A7 non-secure contexts. It therefore cannot be assigned but, it manages all the peripherals assigned to those contexts.
4 How to go further
Refer to Arm website for more detailed information on this core.