Clock device tree configuration

Applicable for

STM32MP13x lines  STM32MP15x lines    STM32MP23x lines  STM32MP25x lines

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1. Article purpose

The purpose of this article is to explain how to configure the RCC internal peripheral clocks using the device tree mechanism, relying on the bindings documentation, that is the description of the required and optional device-tree properties.

The peripheral can be assigned to different contexts/software components, depending on the final product needs. Refer to How to assign an internal peripheral to an execution context article for guidelines on this configuration .

2. DT bindings documentation

The device tree binding documents are stored either in the given applicable components listed below, or in the Linux kernel repository:

• TF-A BL2 and TF-A BL31:
  • for STM32MP13x lines  docs/devicetree/bindings/clock/st,stm32mp13-rcc.txt
  • for STM32MP15x lines  docs/devicetree/bindings/clock/st,stm32mp1-rcc.txt
  • for STM32MP2 series see OP-TEE binding

• OP-TEE:
  • for STM32MP1 series documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
  • for STM32MP2 series documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml

• U-Boot, Linux^® OS:
  • for STM32MP1 series Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
  • for STM32MP2 series Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml

3. DT configuration

This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the Device tree for an explanation of the device-tree file organization.

STM32CubeMX can be used to generate the board device tree. Refer to How to configure the DT using STM32CubeMX for more details.

3.1. DT configuration (STM32/SoC level)

The RCC node is located in the device tree file for the software components, supporting the peripheral and listed in the above DT bindings documentation paragraph.

Warning

This device tree part is related to STM32 microprocessors. It must be kept as is, without being modified by the end-user.

3.2. DT configuration (board level)

The objective of this chapter is to explain how to configure a clock tree related to the board.

Using this chapter, the end-user can configure any parameters via the DT to adapt to a new board.

3.2.1. STM32MP13x lines 

Clock tree configuration it's done in TF-A and in OP-TEE.

See "how to build a clock tree" in STM32MP13_clock_tree.

Usually a minimal configuration is applied in TF-A BL2 and the full configuration in OP-TEE.

This an example a clock configuration tree:

&rcc {
	st,clksrc = <
		CLK_MPU_PLL1P
		CLK_AXI_PLL2P
		CLK_MLAHBS_PLL3
		CLK_RTC_LSE
		CLK_MCO1_HSE
		CLK_MCO2_DISABLED
		CLK_CKPER_HSE
		CLK_ETH1_PLL4P
		CLK_ETH2_PLL4P
		CLK_SDMMC1_PLL4P
		CLK_SDMMC2_PLL4P
		CLK_STGEN_HSE
		CLK_USBPHY_HSE
		CLK_I2C4_HSI
		CLK_I2C5_HSI
		CLK_USBO_USBPHY
		CLK_ADC2_CKPER
		CLK_I2C12_HSI
		CLK_UART1_HSI
		CLK_UART2_HSI
		CLK_UART35_HSI
		CLK_UART4_HSI
		CLK_UART6_HSI
		CLK_UART78_HSI
		CLK_SAES_AXI
		CLK_DCMIPP_PLL2Q
		CLK_LPTIM3_PCLK3
		CLK_RNG1_PLL4R
	>;

	st,clkdiv = <
		DIV(DIV_MPU, 1)
		DIV(DIV_AXI, 0)
		DIV(DIV_MLAHB, 0)
		DIV(DIV_APB1, 1)
		DIV(DIV_APB2, 1)
		DIV(DIV_APB3, 1)
		DIV(DIV_APB4, 1)
		DIV(DIV_APB5, 2)
		DIV(DIV_APB6, 1)
		DIV(DIV_RTC, 0)
		DIV(DIV_MCO1, 0)
		DIV(DIV_MCO2, 0)
	>;

	st,pll_vco {
		pll1_vco_2000MHz: pll1-vco-2000Mhz {
			src = <CLK_PLL12_HSE>;
			divmn = <1 82>;
			frac = <0xAAA>;
		};

		pll1_vco_1300Mhz: pll1-vco-1300Mhz {
			src = <CLK_PLL12_HSE>;
			divmn = <2 80>;
			frac = <0x800>;
		};

		pll2_vco_1066Mhz: pll2-vco-1066Mhz {
			src = <CLK_PLL12_HSE>;
			divmn = <2 65>;
			frac = <0x1400>;
		};

		pll3_vco_417Mhz: pll3-vco-417Mhz {
			src = <CLK_PLL3_HSE>;
			divmn = <1 33>;
			frac = <0x1a04>;
		};

		pll4_vco_600Mhz: pll4-vco-600Mhz {
			src = <CLK_PLL4_HSE>;
			divmn = <1 49>;
		};
	};

	/* VCO = 1300.0 MHz => P = 650 (CPU) */
	pll1: st,pll@0 {
		compatible = "st,stm32mp1-pll";
		reg = <0>;

		st,pll = <&pll1_cfg1>;

		pll1_cfg1: pll1_cfg1 {
			st,pll_vco = <&pll1_vco_1300Mhz>;
			st,pll_div_pqr = <0 1 1>;
		};

		pll1_cfg2: pll1_cfg2 {
			st,pll_vco = <&pll1_vco_2000Mhz>;
			st,pll_div_pqr = <0 1 1>;
		};
	};

	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */
	pll2: st,pll@1 {
		compatible = "st,stm32mp1-pll";
		reg = <1>;

		st,pll = <&pll2_cfg1>;

		pll2_cfg1: pll2_cfg1 {
			st,pll_vco = <&pll2_vco_1066Mhz>;
			st,pll_div_pqr = <1 1 0>;
		};
	};

	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
	pll3: st,pll@2 {
		compatible = "st,stm32mp1-pll";
		reg = <2>;

		st,pll = <&pll3_cfg1>;

		pll3_cfg1: pll3_cfg1 {
			st,pll_vco = <&pll3_vco_417Mhz>;
			st,pll_div_pqr = <1 16 36>;
		};
	};

	/* VCO = 600.0 MHz => P = 50, Q = 10, R = 50 */
	pll4: st,pll@3 {
		compatible = "st,stm32mp1-pll";
		reg = <3>;
		st,pll = <&pll4_cfg1>;

		pll4_cfg1: pll4_cfg1 {
			st,pll_vco = <&pll4_vco_600Mhz>;
			st,pll_div_pqr = <11 59 11>;
		};
	};
};

You can find a full example of the board configuration here :

• in TF-A fdts/stm32mp135f-dk.dts
• in OP-TEE core/arch/arm/dts/stm32mp135f-dk.dts

3.2.2. STM32MP15x lines 

Clock tree configuration it's done in TF-A and in OP-TEE.

See "how to build a clock tree" in STM32MP15_clock_tree.

Usually a minimal configuration is applied in TF-A BL2 and the full configuration in OP-TEE.

This an example a clock configuration tree:

&rcc {
	st,clksrc = <
		CLK_MPU_PLL1P
		CLK_AXI_PLL2P
		CLK_MCU_PLL3P
		CLK_RTC_LSE
		CLK_MCO1_DISABLED
		CLK_MCO2_DISABLED
		CLK_CKPER_HSE
		CLK_FMC_ACLK
		CLK_QSPI_ACLK
		CLK_ETH_PLL4P
		CLK_SDMMC12_PLL4P
		CLK_DSI_DSIPLL
		CLK_STGEN_HSE
		CLK_USBPHY_HSE
		CLK_SPI2S1_PLL3Q
		CLK_SPI2S23_PLL3Q
		CLK_SPI45_HSI
		CLK_SPI6_HSI
		CLK_I2C46_HSI
		CLK_SDMMC3_PLL4P
		CLK_USBO_USBPHY
		CLK_ADC_CKPER
		CLK_CEC_LSE
		CLK_I2C12_HSI
		CLK_I2C35_HSI
		CLK_UART1_HSI
		CLK_UART24_HSI
		CLK_UART35_HSI
		CLK_UART6_HSI
		CLK_UART78_HSI
		CLK_SPDIF_PLL4P
		CLK_FDCAN_PLL4R
		CLK_SAI1_PLL3Q
		CLK_SAI2_PLL3Q
		CLK_SAI3_PLL3Q
		CLK_SAI4_PLL3Q
		CLK_RNG1_CSI
		CLK_RNG2_LSI
		CLK_LPTIM1_PCLK1
		CLK_LPTIM23_PCLK3
		CLK_LPTIM45_LSE
	>;

	st,clkdiv = <
		DIV(DIV_MPU, 1)
		DIV(DIV_AXI, 0)
		DIV(DIV_MCU, 0)
		DIV(DIV_APB1, 1)
		DIV(DIV_APB2, 1)
		DIV(DIV_APB3, 1)
		DIV(DIV_APB4, 1)
		DIV(DIV_APB5, 2)
		DIV(DIV_RTC, 23)
		DIV(DIV_MCO1, 0)
		DIV(DIV_MCO2, 0)
	>;

	st,pll_vco {
		pll2_vco_1066Mhz: pll2-vco-1066Mhz {
			src = <CLK_PLL12_HSE>;
			divmn = <2 65>;
			frac = <0x1400>;
		};

		pll3_vco_417Mhz: pll3-vco-417Mhz {
			src = <CLK_PLL3_HSE>;
			divmn = <1 33>;
			frac = <0x1a04>;
		};

		pll4_vco_594Mhz: pll4-vco-594Mhz {
			src = <CLK_PLL4_HSE>;
			divmn = <3 98>;
		};
	};

	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
	pll2: st,pll@1 {
		compatible = "st,stm32mp1-pll";
		reg = <1>;

		st,pll = <&pll2_cfg1>;

		pll2_cfg1: pll2_cfg1 {
			st,pll_vco = <&pll2_vco_1066Mhz>;
			st,pll_div_pqr = <1 0 0>;
		};
	};

	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
	pll3: st,pll@2 {
		compatible = "st,stm32mp1-pll";
		reg = <2>;

		st,pll = <&pll3_cfg1>;

		pll3_cfg1: pll3_cfg1 {
			st,pll_vco = <&pll3_vco_417Mhz>;
			st,pll_div_pqr = <1 16 36>;
		};
	};

	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
	pll4: st,pll@3 {
		compatible = "st,stm32mp1-pll";
		reg = <3>;

		st,pll = <&pll4_cfg1>;

		pll4_cfg1: pll4_cfg1 {
			st,pll_vco = <&pll4_vco_594Mhz>;
			st,pll_div_pqr = <5 7 7>;
		};
	};

You can find a full example of the board configuration here :

• in T-FA : fdts/stm32mp157c-ed1.dts
• in OP-TEE : core/arch/arm/dts/stm32mp157c-ed1.dts

3.2.3. STM32MP2 series

Clock tree configuration it's done in TF-A and in OP-TEE.

See "how to build a clock tree" in STM32MP25_clock_tree.

Usually a minimal configuration is applied in TF-A BL2 and the full configuration in OP-TEE.

This an example a clock configuration tree:

&rcc {
	st,busclk = <
		DIV_CFG(DIV_LSMCU, 1)
		DIV_CFG(DIV_APB1, 0)
		DIV_CFG(DIV_APB2, 0)
		DIV_CFG(DIV_APB3, 0)
		DIV_CFG(DIV_APB4, 0)
		DIV_CFG(DIV_APBDBG, 0)
	>;

	st,flexgen = <
		FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 2)
		FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5)
		FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1)
		FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3)
		FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2)
		FLEXGEN_CFG(8, XBAR_SRC_PLL4, 0, 11)
		FLEXGEN_CFG(48, XBAR_SRC_PLL5, 0, 3)
		FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5)
		FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5)
		FLEXGEN_CFG(58, XBAR_SRC_HSE, 0, 1)
		FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2)
	>;

	st,kerclk = <
		MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57)
		MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58)
	>;

	pll1: st,pll-1 {
		st,pll = <&pll1_cfg_1200Mhz>;

		pll1_cfg_1200Mhz: pll1-cfg-1200Mhz {
			cfg = <30 1 1 1>;
			src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
		};
	};

	/* DRAM clock = 2 * PLL2 clock */
	pll2: st,pll-2 {
		st,pll = <&pll2_cfg_600Mhz>;

		pll2_cfg_600Mhz: pll2-cfg-600Mhz {
			cfg = <30 1 1 2>;
			src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>;
		};
	};

	pll4: st,pll-4 {
		st,pll = <&pll4_cfg_1200Mhz>;

		pll4_cfg_1200Mhz: pll4-cfg-1200Mhz {
			cfg = <30 1 1 1>;
			src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>;
		};
	};

	pll5: st,pll-5 {
		st,pll = <&pll5_cfg_532Mhz>;

		pll5_cfg_532Mhz: pll5-cfg-532Mhz {
			cfg = <133 5 1 2>;
			src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>;
		};
	};
};

You can find a full example of the board configuration here :

• in TF-A fdts/stm32mp257f-ev1-ca35tdcid-rcc.dtsi
• in OP-TEE core/arch/arm/dts/stm32mp257f-ev1-ca35tdcid-rcc.dtsi

In addition, RCC is a RIF-aware peripheral and it is possible to assign RCC clocks to different execution contexts.
RCC RIF configuration must be done by the Secure OS of the main processor (TDCID).
A specific binding is used in OP-TEE device tree to set RIF configuration at boot time, by defining the st,protreg property. It is defined at board level:

Please find below assignment example:

&rcc {
	st,protreg = <
		RIFPROT(RIF_RCC_RESOURCE(69), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
		RIFPROT(RIF_RCC_RESOURCE(64), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
		RIFPROT(RIF_RCC_RESOURCE(65), RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
		...
	>;
};

You can find a full example of the board configuration here :

• in OP-TEE core/arch/arm/dts/stm32mp257f-ev1-ca35tdcid-rif.dtsi

4. How to configure the DT using STM32CubeMX

The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.
STM32CubeMX may not support all the properties described in DT binding files listed in the above DT bindings documentation paragraph. If so, the tool inserts user sections in the generated device tree. These sections can then be edited to add some properties, and they are preserved from one generation to another. Refer to STM32CubeMX user manual for further information.

5. References

Please refer to the following links for additional information:

Device tree

Linux^® is a registered trademark of Linus Torvalds.

Trusted firmware for Arm^® Cortex^®-A

Boot loader stage 2

Open portable trusted execution environment

Das U-Boot -- the universal boot loader (see U-Boot)

Operating system

Microprocessor unit

Real time clock

Low speed external oscillator (STM32 clock source)

High speed external oscillator (STM32 clock source)

System time generator

High speed internal oscillator (STM32 clock source) or High speed synchronous serial interface (MIPI^® Alliance standard)

Digital Camera memory interface pixel processor

Central processing unit

Doubledata rate (memory domain)

Microcontroller unit (MCUs have internal flash memory and are intended to operate with a minimum amount of external support ICs. They commonly are a self-contained, system-on-chip (SoC) designs.)

Ethernet

Display serial interface (MIPI^® Alliance standard)

Analog-to-digital converter. The process of converting a sampled analog signal to a digital code that represents the amplitude of the original signal sample.

Consumer electronics control (HDMI standard)

Multi Speed Internal oscillator (STM32 clock source)

Low speed internal oscillator (STM32 clock source)

Graphics processing units

Reset and clock control

Resource Isolation Framework

Trusted Domain Compartment IDentifier - NEW

Device tree

Linux^® is a registered trademark of Linus Torvalds.

Trusted firmware for Arm^® Cortex^®-A

Boot loader stage 2

Open portable trusted execution environment

Das U-Boot -- the universal boot loader (see U-Boot)

Operating system

Microprocessor unit

Real time clock

Low speed external oscillator (STM32 clock source)

High speed external oscillator (STM32 clock source)

System time generator

High speed internal oscillator (STM32 clock source) or High speed synchronous serial interface (MIPI^® Alliance standard)

Digital Camera memory interface pixel processor

Central processing unit

Doubledata rate (memory domain)

Microcontroller unit (MCUs have internal flash memory and are intended to operate with a minimum amount of external support ICs. They commonly are a self-contained, system-on-chip (SoC) designs.)

Ethernet

Display serial interface (MIPI^® Alliance standard)

Analog-to-digital converter. The process of converting a sampled analog signal to a digital code that represents the amplitude of the original signal sample.

Consumer electronics control (HDMI standard)

Multi Speed Internal oscillator (STM32 clock source)

Low speed internal oscillator (STM32 clock source)

Graphics processing units

Reset and clock control

Resource Isolation Framework

Trusted Domain Compartment IDentifier - NEW

Arm^® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Cortex^®

Mobile Industry Processor Interface, open membership organization that includes leading companies in the mobile industry that share the objective of defining and promoting open specifications for interfaces inside mobile terminals, see MIPI^® Alliance standard web site https://www.mipi.org

High-definition multimedia interface (HDMI standard)