Last edited 5 months ago

DDRPERFM internal peripheral


1. Article purpose

The purpose of this article is to:

  • briefly introduce the DDRPERFM peripheral and its main features,
  • indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
  • list the software frameworks and drivers managing the peripheral,
  • explain how to configure the peripheral.

2. Peripheral overview

The DDRPERFM peripheral is used to count various DDRCTRL events, for performance analysis.

The read, write and time counters are certainly the ones that are the most useful from user point of view, since they allow computing the DDR read and write throughputs.

Other counters are available in order to monitor the DDR controller arbitration dynamic, refresh commands and low-power management.

Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.

3. Peripheral usage

This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm® Cortex®-A processor(s), and the STM32CubeMPU Package running on the Arm® Cortex®-M processor.

3.1. Boot time assignment

3.1.1. On STM32MP1 series

The DDRPERFM peripheral is not used at boot time.

3.1.2. On STM32MP2 series

Click on How to.png to expand or collapse the legend...

Domain Peripheral Boot time allocation Comment How to.png
Instance Cortex-A35
secure
(ROM code)
Cortex-A35
secure
(TF-A BL2)
Cortex-A35
nonsecure
(U-Boot)
Trace & Debug DDRPERFM DDRPERFM

3.2. Runtime assignment

3.2.1. On STM32MP13x lines More info.png

Click on How to.png to expand or collapse the legend...

Domain Peripheral Runtime allocation Comment How to.png
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Trace & Debug DDRPERFM DDRPERFM

3.2.2. On STM32MP15x lines More info.png

Click on How to.png to expand or collapse the legend...

Domain Peripheral Runtime allocation Comment How to.png
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Trace & Debug DDRPERFM DDRPERFM

3.2.3. On STM32MP21x lines More info.png

Click on How to.png to expand or collapse the legend...

Domain Peripheral Runtime allocation Comment How to.png
Instance Cortex-A35
secure
(OP-TEE /
TF-A BL31)
Cortex-A35
nonsecure
(Linux)
Cortex-M33
secure
(TF-M)
Cortex-M33
nonsecure
(STM32Cube)
Trace & Debug DDRPERFM DDRPERFM OP-TEE Part of DDRSS protected by RCC DDRPERFM_CFGR

3.2.4. On STM32MP23x lines More info.png

Click on How to.png to expand or collapse the legend...

Domain Peripheral Runtime allocation Comment How to.png
Instance Cortex-A35
secure
(OP-TEE /
TF-A BL31)
Cortex-A35
nonsecure
(Linux)
Cortex-M33
secure
(TF-M)
Cortex-M33
nonsecure
(STM32Cube)
Trace & Debug DDRPERFM DDRPERFM OP-TEE Part of DDRSS protected by RCC DDR_CFGR

3.2.5. On STM32MP25x lines More info.png

Click on How to.png to expand or collapse the legend...

Domain Peripheral Runtime allocation Comment How to.png
Instance Cortex-A35
secure
(OP-TEE /
TF-A BL31)
Cortex-A35
nonsecure
(Linux)
Cortex-M33
secure
(TF-M)
Cortex-M33
nonsecure
(STM32Cube)
Cortex-M0+
(STM32Cube)
Trace & Debug DDRPERFM DDRPERFM OP-TEE Part of DDRSS protected by RCC DDR_CFGR

4. Software frameworks and drivers

Below are listed the software frameworks and drivers managing the DDRPERFM peripheral for the embedded software components listed in the above tables.

5. How to assign and configure the peripheral

The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:

  • partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
  • HAL initialization code generation for the STM32CubeMPU Package.

The configuration is applied by the firmware running in the context in which the peripheral is assigned.

6. How to go further

Refer to How to measure the DDR throughput to learn how to use the DDRPERFM internal peripheral via the perf tool.