- Last edited 3 weeks ago ago
STM32MP13 ecosystem errata sheet
1 Article purpose
The STM32MP13xx device errata sheet lists the different device limitations and explains the corresponding workarounds (software and/or hardware) if any.
The objective of this article is to explain which of the workarounds, described in this errata sheet, are applicable and implemented in ecosystem release v4.1.0 .
This article lists
- errata to be workaround by the customers,
- errata workaround implemented in STM32MPU Ecosystem releases,
- and errata not applicable in STM32MPU Ecosystem releases.
Errata, present in STM32MP13xx device errata sheet and not listed in this article, have no workaround implemented in STM32MPU Ecosystem releases.
The section column refers to the number of the erratum chapter in the errata sheet document.
Rev.Y columns , present in the tables below, refer to the availability and status of a given errata workaround for the described erratum in errata sheet document:
- A = workaround available
- P = partial workaround available
- N = no workaround available
OpenSTLinux and CubeMP1 columns , present in the tables below, refer to the availability of a workaround for a given STM32MP13 ecosystem release:
- U = workaround to implement by User
- I = workaround Implemented
- NA= Errata Not Applicable in ST software release
Wave your mouse over a status in the table to display the corresponding legend.
3 Workarounds to implement by customer
|Arm® Cortex®-A7 core||2.1.1||Memory locations might be accessed speculatively due to instruction fetches when HCR.VM is set||A||U||NA||OpenSTLinux distribution does not activate Arm® Cortex®-A7 Hypervisor mode and hence the Virtual Memory second stage of translation.|
The customer should implement the workaround if the Hypervisor mode is used in his/her product.
|DMAMUX||2.3.4||Wrong input DMA request routed upon specific DMAMUX_CxCR register write coinciding with synchronization event||A||NA||U||STM32CubeMP1_Package: The customer should provide the right DMAMUX signal polarity configuration when calling the HAL_DMAEx_ConfigMuxSync() function provided in STM32CubeMP1_Package Src/stm32mp1xx_hal_dma_ex.c .|
|FMC||2.4.1||NOR Flash memory/PSRAM incorrect bus turnaround timing||A||U||OpenSTLinux distribution: Delays to applied by customer device tree.|
|ADC||2.6.8||ADC_AWDy_OUT reset by non-guarded channels||A||U||U||OpenSTLinux distribution: The customer should implement this workaround by configuring only ADC channels that are guarded by a watchdog in the device tree
STM32CubeMP1_Package: The customer should implement this workaround by configuring only ADC channels that are guarded by a watchdog in the application.
|LPTIM||2.9.1||Device may remain stuck in LPTIM interrupt when entering Stop mode||A||NA||U||OpenSTLinux distribution: The LPTIM interrupt is not used. |
STM32CubeMP1_Package: The customer should implement this workaround in MspDeinit().
4 Workarounds implemented in STM32MP13 ecosystem releases
|Arm® Cortex®-A7 core||2.1.2||Cache maintenance by set/way operations can execute out of order||A||I||NA||OpenSTLinux distribution: Implementation accepted by the community since Linux® kernel v5.3 in arch/arm/Kconfig (refer to ARM_ERRATA_814220).|
|System||2.2.2||Incorrect reset of glitch-free kernel clock switch||P||I||OpenSTLinux distribution: By default, STPMIC1 performs a VDDCORE reset on NRST activation.|
|2.2.3||SAES, RNG, PKA stuck after first stage bootloader (FSBL) decryption||A||U||NA||OpenSTLinux distribution: the enabling of SAES is handled within TF-A. When another FSBL is used the SAES clock should be enabled in the customer software, even if SAES is not.|
|QUADSPI||2.5.1||Memory-mapped read of last memory byte fails||P||I|
|DTS||2.7.1||DTS incorrect operation with LSE as reference clock and PCLK enabled||P||I|
|LPTIM||2.9.2||MCU may remain stuck in LPTIM interrupt when clearing event flag||P||NA||I|
|I2C||2.11.1||Wrong data sampling when data setup time (tSU;DAT) is shorter than one I2C kernel clock period||P||I||I||OpenSTLinux distribution: Workaround implemented in device tree with a clock tree that configures the I2C kernel clock source to a frequency higher than 20 MHz.|
|SPI||2.13.1||Master data transfer stall at system clock much faster than SCK||A||I||I||OpenSTLinux distribution: SPI is disabled after each EOT
STM32CubeMP1_Package: SPI is disabled after each EOT.
|2.13.3||TXP interrupt occurring while SPI disabled||A||I||I||OpenSTLinux distribution: all interrupts are disabled before the SPI is disabled.|
|ETH||2.16.6||ARP offload function not effective||A||I|
5 Workarounds not applicable in STM32MP13 ecosystem releases
|DMAMUX||2.3.1||SOFx not asserted when writing into DMAMUX_CFR register||N||NA||OpenSTLinux distribution: DMA synchronization event is not used.|
|2.3.2||OFx not asserted for trigger event coinciding with last DMAMUX request||N||NA||OpenSTLinux distribution: DMA Trigger event is not used.|
|2.3.3||OFx not asserted when writing into DMAMUX_RGCFR register||N||NA||OpenSTLinux distribution: DMA Trigger event is not used.|
|2.3.4||Wrong input DMA request routed upon specific DMAMUX_CxCR register write coinciding with synchronization event||A||NA||U||OpenSTLinux distribution: DMA synchronization event is not used.|
|FMC||2.4.2||Incorrect FMC_CLK clock period when CLKDIV value is changed on-the-fly in continuous clock mode||A||NA||OpenSTLinux distribution: CLKDIV can't be changed on-the-fly.|
|2.4.3||NAND Flash memory IREF/IFEF flags wrongly asserted just after enabling in FMC_IER||A||NA||OpenSTLinux distribution: IREF/IFEF flags are not used.|
|2.4.4||Command sequencer accesses NAND Flash memory device while PBKEN bit is cleared in FMC_PCR||A||NA||OpenSTLinux distribution: PBKEN bit is set at probe time and never cleared on the flag.|
|2.4.5||NAND Flash memory IREF flag wrongly asserted after reset||A||NA|
|ADC||2.6.1||Injected queue of context is not available if JQM = 0||N||NA||OpenSTLinux distribution: Injected conversion not implemented.|
|2.6.2||Sampling time shortened in JAUTO auto delayed mode||A||NA||OpenSTLinux distribution: Injected conversion not implemented.|
|2.6.5||New context conversion initiated without waiting for trigger when writing new context in ADC_JSQR with JQDIS = 0 and JQM = 0||A||NA||OpenSTLinux distribution: JQDIS = 1, this issue occurs only when JQDIS = 0.|
|2.6.6||Two consecutive context conversions fail when writing new context in ADC_JSQR just after previous context completion with JQDIS = 0 and JQM = 0||A||NA||OpenSTLinux distribution: JQDIS = 1, this issue occurs only when JQDIS = 0.|
|2.6.7||Unexpected regular conversion when two consecutive injected conversions are performed in Dual interleaved mode||A||NA||OpenSTLinux distribution: Dual mode is not implemented.|
|2.6.9||Injected data stored in the wrong ADC_JDRx registers||A||NA||OpenSTLinux distribution: Injected conversion not implemented.|
|2.6.10||ADC slave data may be shifted in Dual regular simultaneous mode||A||NA||OpenSTLinux distribution: Dual mode is not implemented.|
|LPTIM||2.9.1||Device may remain stuck in LPTIM interrupt when entering Stop mode||A||NA||U||OpenSTLinux distribution: LPTIM interrupt is not used|
|2.9.2||MCU may remain stuck in LPTIM interrupt when clearing event flag||P||NA||I||OpenSTLinux distribution: LPTIM interrupt is not used|
|RTC and TAMP||2.10.2||Binary mode: SSR is not reloaded with 0xFFFF FFFF when SSCLR = 1||A||NA||OpenSTLinux distribution: Binary mode is not used|
|USART||2.12.1||Anticipated end-of-transmission signaling in SPI slave mode||A||NA||OpenSTLinux distribution: SPI slave mode is not implemented|
|SPI||2.13.2||Corrupted CRC return at non-zero UDRDET setting||P||NA||OpenSTLinux distribution: CRC is not supported|
|2.13.4||Possible corruption of last-received data depending on CRCSIZE setting||A||NA||OpenSTLinux distribution: CRC is not supported|