1. Article purpose[edit | edit source]
The STM32MP13xx device errata sheet[1] lists the different device limitations and explains the corresponding workarounds (software and/or hardware) if any.
The objective of this article is to explain which of the workarounds, described in this errata sheet, are applicable and implemented in ecosystem release v4.1.0 .
This article lists
- errata to be workaround by the customers,
- errata workaround implemented in STM32MPU Ecosystem releases,
- and errata not applicable in STM32MPU Ecosystem releases.
Errata, present in STM32MP13xx device errata sheet[1] and not listed in this article, have no workaround implemented in STM32MPU Ecosystem releases.
2. Legend[edit | edit source]
The section column refers to the number of the erratum chapter in the errata sheet document.
Rev.Y columns , present in the tables below, refer to the availability and status of a given errata workaround for the described erratum in errata sheet document:
- A = workaround available
- P = partial workaround available
- N = no workaround available
OpenSTLinux and CubeMP1 columns , present in the tables below, refer to the availability of a workaround for a given STM32MP13 ecosystem release:
- U = workaround to implement by User
- I = workaround Implemented
- NA= Errata Not Applicable in ST software release
Wave your mouse over a status in the table to display the corresponding legend.
3. Workarounds to implement by customer[edit | edit source]
| Function | Section | Limitation | Rev.Y | 
|
|
Comment |
|---|---|---|---|---|---|---|
| Arm® Cortex®-A7 core | 2.1.1 | Memory locations might be accessed speculatively due to instruction fetches when HCR.VM is set | A | U | NA | OpenSTLinux distribution does not activate Arm® Cortex®-A7 Hypervisor mode and hence the Virtual Memory second stage of translation. The customer should implement the workaround if the Hypervisor mode is used in his/her product. |
| System | 2.2.3 | SAES, RNG, PKA stuck after first stage bootloader (FSBL) decryption | A | U | NA | OpenSTLinux distribution: The enabling of SAES is handled within TF-A in OpenSTLinux.
STM32CubeMP13_Package: When another FSBL is used the SAES clock should be enabled in the customer software, even if SAES is not. |
| DMAMUX | 2.4.4 | Wrong input DMA request routed upon specific DMAMUX_CxCR register write coinciding with synchronization event | A | NA | U | STM32CubeMP13_Package: The customer should provide the right DMAMUX signal polarity configuration when calling the HAL_DMAEx_ConfigMuxSync() function provided in STM32CubeMP13_Package Src/stm32mp1xx_hal_dma_ex.c . |
| FMC | 2.5.1 | NOR Flash memory/PSRAM incorrect bus turnaround timing | A | U | OpenSTLinux distribution: Delays to applied by customer device tree. | |
| ADC | 2.8.4 | ADC_AWDy_OUT reset by non-guarded channels | A | U | U | OpenSTLinux distribution: The customer should implement this workaround by configuring only ADC channels that are guarded by a watchdog in the device tree
STM32CubeMP13_Package: The customer should implement this workaround by configuring only ADC channels that are guarded by a watchdog in the application. |
| LPTIM | 2.14.1 | Device may remain stuck in LPTIM interrupt when entering Stop mode | A | NA | U | OpenSTLinux distribution: The LPTIM interrupt is not used. STM32CubeMP13_Package: The customer should implement this workaround in MspDeinit(). |
| I2C | 2.16.2 | Spurious bus error detection in master mode | A | U | U | OpenSTLinux distribution: The LPTIM interrupt is not used.
STM32CubeMP13_Package: Issue visible only in interrupt mode, not in DMA mode. Bus Error should be handled by a Timeout at application level.). |
4. Workarounds implemented in STM32MP13 ecosystem releases[edit | edit source]
| Function | Section | Limitation | Rev.Y |
|
|
Comment |
|---|---|---|---|---|---|---|
| Arm® Cortex®-A7 core | 2.1.2 | Cache maintenance by set/way operations can execute out of order | A | I | NA | OpenSTLinux distribution: Implementation accepted by the community since Linux® kernel v5.3 in arch/arm/Kconfig (refer to ARM_ERRATA_814220). |
| System | 2.2.2 | Incorrect reset of glitch-free kernel clock switch | P | I | OpenSTLinux distribution: By default, STPMIC1 performs a VDDCORE reset on NRST activation. | |
| 2.2.3 | SAES, RNG, PKA stuck after first stage bootloader (FSBL) decryption | A | U | NA | OpenSTLinux distribution: The enabling of SAES is handled within TF-A in OpenSTLinux.
STM32CubeMP13_Package: When another FSBL is used the SAES clock should be enabled in the customer software, even if SAES is not. | |
| QUADSPI | 2.6.1 | Memory-mapped read of last memory byte fails | P | I | ||
| DTS | 2.9.1 | DTS incorrect operation with LSE as reference clock and PCLK enabled | P | I | ||
| LPTIM | 2.14.2 | MCU may remain stuck in LPTIM interrupt when clearing event flag | P | NA | I | |
| I2C | 2.16.1 | Wrong data sampling when data setup time (tSU;DAT) is shorter than one I2C kernel clock period | P | I | I | OpenSTLinux distribution: Workaround implemented in device tree with a clock tree that configures the I2C kernel clock source to a frequency higher than 20 MHz. |
| SPI | 2.19.1 | Master data transfer stall at system clock much faster than SCK | A | I | I | OpenSTLinux distribution: SPI is disabled after each EOT
STM32CubeMP13_Package: SPI is disabled after each EOT. |
| 2.19.3 | TXP interrupt occurring while SPI disabled | A | I | I | OpenSTLinux distribution: all interrupts are disabled before the SPI is disabled. | |
| ETH | 2.22.2 | Rx DMA may fail to recover upon DMA restart following a bus error, with Rx timestamping enabled | A | I | OpenSTLinux distribution: Workaround is implemented in stmmac driver. When a bus error is detected, a SW reset is done and all the descriptors are cleared (Rx and Tx), the queues and descriptors are reinitialized | |
| 2.22.6 | ARP offload function not effective | A | I | |||
| 2.22.9 | DMA spurious state upon AXI DMA slave bus error | P | I | OpenSTLinux distribution: Workaround is implemented is stmmac drive |
5. Workarounds not applicable in STM32MP13 ecosystem releases[edit | edit source]
| Function | Section | Limitation | Rev.Y |
|
|
Comment |
|---|---|---|---|---|---|---|
| DMAMUX | 2.4.1 | SOFx not asserted when writing into DMAMUX_CFR register | N | NA | OpenSTLinux distribution: DMA synchronization event is not used. | |
| 2.4.2 | OFx not asserted for trigger event coinciding with last DMAMUX request | N | NA | OpenSTLinux distribution: DMA Trigger event is not used. | ||
| 2.4.3 | OFx not asserted when writing into DMAMUX_RGCFR register | N | NA | OpenSTLinux distribution: DMA Trigger event is not used. | ||
| 2.4.4 | Wrong input DMA request routed upon specific DMAMUX_CxCR register write coinciding with synchronization event | A | NA | U | OpenSTLinux distribution: DMA synchronization event is not used. | |
| FMC | 2.5.2 | Incorrect FMC_CLK clock period when CLKDIV value is changed on-the-fly in continuous clock mode | A | NA | OpenSTLinux distribution: CLKDIV can't be changed on-the-fly. | |
| 2.5.3 | NAND Flash memory IREF/IFEF flags wrongly asserted just after enabling in FMC_IER | A | NA | OpenSTLinux distribution: IREF/IFEF flags are not used. | ||
| 2.5.4 | Command sequencer accesses NAND Flash memory device while PBKEN bit is cleared in FMC_PCR | A | NA | OpenSTLinux distribution: PBKEN bit is set at probe time and never cleared on the flag. | ||
| 2.5.5 | NAND Flash memory IREF flag wrongly asserted after reset | A | NA | |||
| ADC | 2.8.1 | New context conversion initiated without waiting for trigger when writing new context in ADC_JSQR with JQDIS = 0 and JQM = 0 | A | NA | OpenSTLinux distribution: JQDIS = 1, this issue occurs only when JQDIS = 0. | |
| 2.8.2 | Two consecutive context conversions fail when writing new context in ADC_JSQR just after previous context completion with JQDIS = 0 and JQM = 0 | A | NA | OpenSTLinux distribution: JQDIS = 1, this issue occurs only when JQDIS = 0. | ||
| 2.8.3 | Unexpected regular conversion when two consecutive injected conversions are performed in Dual interleaved mode | A | NA | OpenSTLinux distribution: Dual mode is not implemented. | ||
| 2.8.5 | Injected data stored in the wrong ADC_JDRx registers | A | NA | OpenSTLinux distribution: Injected conversion not implemented. | ||
| 2.8.6 | ADC slave data may be shifted in Dual regular simultaneous mode | A | NA | OpenSTLinux distribution: Dual mode is not implemented. | ||
| SDMMC | 2.7.1 | Command response and receive data end bits not checked | N | NA | NA | Not an issue from SW side as not visible by the SW. |
| LPTIM | 2.14.1 | Device may remain stuck in LPTIM interrupt when entering Stop mode | A | NA | U | OpenSTLinux distribution: LPTIM interrupt is not used |
| 2.14.2 | MCU may remain stuck in LPTIM interrupt when clearing event flag | P | NA | I | OpenSTLinux distribution: LPTIM interrupt is not used | |
| RTC and TAMP | 2.15.2 | Binary mode: SSR is not reloaded with 0xFFFF FFFF when SSCLR = 1 | A | NA | OpenSTLinux distribution: Binary mode is not used | |
| USART | 2.17.1 | Anticipated end-of-transmission signaling in SPI slave mode | A | NA | OpenSTLinux distribution: SPI slave mode is not implemented | |
| 2.17.3 | Received data may be corrupted upon clearing the ABREN bit | A | NA | OpenSTLinux distribution: Condition never reached in Linux OS thanks to the specific implementation (ABREN bit never cleaned up in USART_CR2 register). | ||
| 2.17.4 | Noise error flag set while ONEBIT is set | A | NA | OpenSTLinux distribution: Not applicable as Linux Framework doesn't handle the Noise error indication. | ||
| SPI | 2.19.2 | Corrupted CRC return at non-zero UDRDET setting | P | NA | OpenSTLinux distribution: CRC is not supported | |
| 2.19.4 | Possible corruption of last-received data depending on CRCSIZE setting | A | NA | OpenSTLinux distribution: CRC is not supported | ||
| I2C | 2.16.4 | Transmission stalled after first byte transfer | P | NA | OpenSTLinux distribution: Condition never reached in Linux OS thanks to the specific implementation (TXDR always filled before transmission). | |
| ETH | 2.22.3 | Spurious receive watchdog timeout interrupt | A | NA | OpenSTLinux distribution: This bug does not affect OpenSTLinux because of the specific implementation of the driver. | |
| 2.22.10 | Incorrect DMA transfer state in TEB[2:0] and REB[2:0] on bus error | A | NA | OpenSTLinux distribution: No functional impact because only the DMA transfer state is incorrect. | ||
| 2.22.12 | Fatal bus error interrupt not generated when the descriptor posted write is enabled | A | NA | OpenSTLinux distribution: No impact as the register DSPW bit if the ETH_DMAMR register is never used in dwmac driver. It remains set to 0 in any condition. |
6. References[edit | edit source]
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.