Last edited 3 months ago

Ethernet switch device tree configuration

Applicable for STM32MP25x lines


1. Article purpose[edit | edit source]

This article explains how to configure the Ethernet switch when it is assigned to the Linux® OS. In this case, it is controlled by the Ethernet switch driver. The configuration is performed using the device tree mechanism. This provides a hardware description of the Ethernet switch peripheral used by the STM32/TTTech driver.

2. DT bindings documentation[edit | edit source]

The Ethernet switch is a multifunction device.

Each function is represented by a separate binding document:

  • "Generic" Ethernet device tree bindings [1]
  • "Generic" Ethernet switch device tree bindings [2]
  • Specific STM32 DEIP device tree bindings[3]
  • Specific TTTech device tree bindings[4]
including DEIP Core Edge block
including ACM block

3. DT configuration[edit | edit source]

This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the Device tree for an explanation of the device tree file split.

3.1. DT configuration (STM32 level)[edit | edit source]

Ethernet peripheral nodes are located in

  • for STM32MP257 in stm32mp257.dtsi [5] file,

This is a set of properties that may not vary for a given STM32MP device, such as: interrupts, clocks, ... 

  switch0: ttt-sw@4c000000 {
	#address-cells  = <1>;
	#size-cells     = <1>;
	compatible = "st,stm32-deip";
	clock-names = "ethsw-bus-clk", "ethsw-clk",
		      "ethswacmcfg-bus-clk", "ethswacmmsg-bus-clk";
	clocks = <&rcc CK_BUS_ETHSW>,
		 <&rcc CK_KER_ETHSW>,
		 <&rcc CK_BUS_ETHSWACMCFG>,
		 <&rcc CK_BUS_ETHSWACMMSG>;
	st,syscon = <&syscfg 0x3800>;
	ranges = <0x4c000000 0x4c000000 0x2000000>,
		 <0x4b000000 0x4b000000 0xc0000>;
	feature-domains = <&rifsc STM32MP25_RIFSC_ETHSW_DEIP_ID>;
	status = "disabled";

	deip_sw0: deip-sw@4c000000 {
		compatible =  "ttt,deip-sw";
		reg = <0x4c000000 0x2000000>;
		interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
	};

	acm@4b000000 {
		compatible = "ttt,acm-4.0";
		reg = <0x4b000000 0x00400>,
		      <0x4b010000 0x10000>,
		      <0x4b030000 0x10000>,
		      <0x4b050000 0x10000>,
		      <0x4b060000 0x20000>,
		      <0x4b080000 0x40000>;
		reg-names = "CommonRegister",
			    "Bypass1",
			    "Bypass0",
			    "Redundancy",
			    "Scheduler",
			    "Messagebuffer";
		buffers = <32>;
		ptp_worker = <&deip_sw0>;
	};
  };
Warning white.png Warning
This device tree part is related to STM32 microprocessors. It must be kept as is, without being modified by the end-user.

3.2. Ethernet DT configuration (board level)[edit | edit source]

Warning white.png Warning
These DT are same between U-Boot and kernel OS

The device tree board file (.dts) contains all hardware configurations related to board design. The DT node ("ethernet") must be updated to:

  • Enable the Ethernet block by setting status = "okay".
  • Configure the pins in use via pinctrl, through pinctrl-0 and pinctrl-names.
  • Configure Ethernet interface used phy-mode = "rgmii"., correspond to internal port sw0p1, port between GMAC IP and Switch. (do not change it)

3.2.1. DT configuration with rcc clock[edit | edit source]

 &eth1 {
    status = "okay";                                 /* enable eth1 */ 
    pinctrl-0 = <&eth1_mdio_pins_a>;    /* configure pinctrl mdio/mdc for eth1 */
    pinctrl-names = "default";
    phy-mode = "rgmii";                          /* configure ethernet phy mode for eth1 */
    st,eth-clk-sel;
    snps,ext-systime;
    fixed_link: fixed-link {                        /* configure ethernet fixed-link for eth1 */ 
    	speed = <1000>;                           /* configure ethernet max speed for fixed link */ 
    	full-duplex;
    };
    mdio1 {
    	#address-cells = <1>;
       #size-cells = <0>;
    	compatible = "snps,dwmac-mdio";
       phy1_eth1: ethernet-phy@4 {
    	      compatible = "ethernet-phy-id001c.c916",
    			     "ethernet-phy-ieee802.3-c22";
             realtek,eee-disable;
             reg = <4>;                                 /* configure ethernet phy 1 @ for eth1 */
       };
       phy2_eth1: ethernet-phy@5 {
    	      compatible = "ethernet-phy-id001c.c916",
    			    "ethernet-phy-ieee802.3-c22";
    	      reset-gpios =  <&gpioj 9 GPIO_ACTIVE_LOW>;
    	      reset-assert-us = <10000>;
    	      reset-deassert-us = <80000>;
    	      realtek,eee-disable;
    	      reg = <5>;                                /* configure ethernet phy 2 @ for eth1 */
       };
    };
 };
 &switch0 {
   status = "okay";
   pinctrl-0 = <&eth1_rgmii_pins_a>, <&eth3_rgmii_pins_a>;   /* configure pinctrl for switch */
   pinctrl-names = "default";
   phy-mode = "rgmii";
   st,ethsw-internal-125;
 };

3.2.2. DT configuration with ETHx_CLK125 phy clock[edit | edit source]

To use the ETHx_CLK125 clock, we need to remove two properties :

  • st,eth-clk-sel : because it is used to set the rcc clock, so it must be removed from the dt
  • st,ethsw-internal-125 : because it acts on bit 2 of the register and is used to check which clock is used with
    • 0: External from ETH1_CLK125 pin
    • 1: Internal from ck_ker_ethsw
 &eth1 {
    status = "okay";                                 /* enable eth1 */ 
    pinctrl-0 = <&eth1_mdio_pins_a>;    /* configure pinctrl mdio/mdc for eth1 */
    pinctrl-names = "default";
    phy-mode = "rgmii";                          /* configure ethernet phy mode for eth1 */
    snps,ext-systime;
    fixed_link: fixed-link {                        /* configure ethernet fixed-link for eth1 */ 
    	speed = <1000>;                           /* configure ethernet max speed for fixed link */ 
    	full-duplex;
    };
    mdio1 {
    	#address-cells = <1>;
       #size-cells = <0>;
    	compatible = "snps,dwmac-mdio";
       phy1_eth1: ethernet-phy@4 {
    	      compatible = "ethernet-phy-id001c.c916",
    			     "ethernet-phy-ieee802.3-c22";
             realtek,eee-disable;
             reg = <4>;                                 /* configure ethernet phy 1 @ for eth1 */
       };
       phy2_eth1: ethernet-phy@5 {
    	      compatible = "ethernet-phy-id001c.c916",
    			    "ethernet-phy-ieee802.3-c22";
    	      reset-gpios =  <&gpioj 9 GPIO_ACTIVE_LOW>;
    	      reset-assert-us = <10000>;
    	      reset-deassert-us = <80000>;
    	      realtek,eee-disable;
    	      reg = <5>;                                /* configure ethernet phy 2 @ for eth1 */
       };
    };
 };
 &switch0 {
   status = "okay";
   pinctrl-0 = <&eth1_rgmii_pins_a>, <&eth3_rgmii_pins_a>;   /* configure pinctrl for switch */
   pinctrl-names = "default";
   phy-mode = "rgmii";
 };

3.3. DT configuration example to transform ethernet switch to ethernet standalone at board level[edit | edit source]

The example below shows how to update devicetree to have eth1 as Ethernet standalone

3.3.1. For rcc clock[edit | edit source]

 &eth1 {
    status = "okay";                                 /* enable eth1 */ 
    pinctrl-0 = <&eth1_mdio_pins_a>;    /* configure pinctrl mdio/mdc for eth1 */
    pinctrl-0 = <&eth1_rgmii_pins_a &eth1_mdio_pins_a>;
    pinctrl-names = "default";
    phy-mode = "rgmii";                          /* configure ethernet phy mode for eth1 */
    phy-mode = "rgmii-id";                          /* configure ethernet phy mode for eth1 */
    st,eth-clk-sel;
    snps,ext-systime;
    fixed_link: fixed-link {                        /* configure ethernet fixed-link for eth1 */ 
    	speed = <1000>;
    	full-duplex;
    };
    phy-handle = <&phy1_eth1>;
    mdio1 {
    	#address-cells = <1>;
       #size-cells = <0>;
    	compatible = "snps,dwmac-mdio";
       phy1_eth1: ethernet-phy@4 {
    compatible = "ethernet-phy-id001c.c916",
    			     "ethernet-phy-ieee802.3-c22";
       compatible = "ethernet-phy-id001c.c916";
             reset-gpios =  <&gpioj 9 GPIO_ACTIVE_LOW>;
             reset-assert-us = <10000>;
             reset-deassert-us = <80000>;
             realtek,eee-disable;
             reg = <4>;                                 /* configure ethernet phy 1 @ for eth1 */
       };
    phy2_eth1: ethernet-phy@5 {
    	      compatible = "ethernet-phy-id001c.c916",
    			    "ethernet-phy-ieee802.3-c22";
    	      realtek,eee-disable;
    	      reg = <5>;                                /* configure ethernet phy 2 @ for eth1 */
       };
    };
 };
 &switch0 {
    status = "okay";
   status = "disabled";
   pinctrl-0 = <&eth1_rgmii_pins_a>, <&eth3_rgmii_pins_a>;   /* configure pinctrl for switch */
   pinctrl-names = "default";
   phy-mode = "rgmii";
   st,ethsw-internal-125;
 };

3.3.2. For ETHx_CLK125 phy clock[edit | edit source]

 &eth1 {
    status = "okay";                                 /* enable eth1 */ 
    pinctrl-0 = <&eth1_mdio_pins_a>;    /* configure pinctrl mdio/mdc for eth1 */
    pinctrl-0 = <&eth1_rgmii_pins_a &eth1_mdio_pins_a>;
    pinctrl-names = "default";
    phy-mode = "rgmii";                          /* configure ethernet phy mode for eth1 */
    phy-mode = "rgmii-id";                          /* configure ethernet phy mode for eth1 */
    snps,ext-systime;
    fixed_link: fixed-link {                        /* configure ethernet fixed-link for eth1 */ 
    	speed = <1000>;
    	full-duplex;
    };
    phy-handle = <&phy1_eth1>;
    mdio1 {
    	#address-cells = <1>;
       #size-cells = <0>;
    	compatible = "snps,dwmac-mdio";
       phy1_eth1: ethernet-phy@4 {
    compatible = "ethernet-phy-id001c.c916",
    			     "ethernet-phy-ieee802.3-c22";
       compatible = "ethernet-phy-id001c.c916";
             reset-gpios =  <&gpioj 9 GPIO_ACTIVE_LOW>;
             reset-assert-us = <10000>;
             reset-deassert-us = <80000>;
             realtek,eee-disable;
             reg = <4>;                                 /* configure ethernet phy 1 @ for eth1 */
       };
    phy2_eth1: ethernet-phy@5 {
    	      compatible = "ethernet-phy-id001c.c916",
    			    "ethernet-phy-ieee802.3-c22";
    	      realtek,eee-disable;
    	      reg = <5>;                                /* configure ethernet phy 2 @ for eth1 */
       };
    };
 };
 &switch0 {
    status = "okay";
   status = "disabled";
   pinctrl-0 = <&eth1_rgmii_pins_a>, <&eth3_rgmii_pins_a>;   /* configure pinctrl for switch */
   pinctrl-names = "default";
   phy-mode = "rgmii";
 };

4. How to configure Ethernet using CubeMX[edit | edit source]

The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.
The STM32CubeMX may not support all the properties described in the above DT bindings documentation paragraph. If so, the tool inserts user sections in the generated device tree. These sections can then be edited to add some properties and they are preserved from one generation to another. Refer to STM32CubeMX user manual for further information.

5. References[edit | edit source]

  1. ↑ Documentation/devicetree/bindings/net/snps%2Cdwmac.yaml
  2. ↑ Documentation/devicetree/bindings/net/ethernet-controller.yaml
  3. ↑ https://github.com/STMicroelectronics/linux.git
  4. ↑ https://github.com/STMicroelectronics/linux.git
  5. ↑ stm32mp257.dtsi


Linux® is a registered trademark of Linus Torvalds.

Operating system

Device tree

Resource Isolation Framework Security Controller - NEW

Generic interrupt controller

Serial peripheral interface

Das U-Boot -- the universal boot loader (see U-Boot)

General-purpose input/output (A realization of open ended transmission between devices on an embedded level. These pins available on a processor can be programmed to be used to either accept input or provide output to external devices depending on user desires and applications requirements.)

Linux® is a registered trademark of Linus Torvalds.

Operating system

Device tree

Resource Isolation Framework Security Controller - NEW

Generic interrupt controller

Serial peripheral interface

Das U-Boot -- the universal boot loader (see U-Boot)

General-purpose input/output (A realization of open ended transmission between devices on an embedded level. These pins available on a processor can be programmed to be used to either accept input or provide output to external devices depending on user desires and applications requirements.)

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