I3C internal peripheral

Applicable for

STM32MP21x lines, STM32MP23x lines, STM32MP25x lines

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Warning

Concerning the STM32MP25x lines , only the boot time assignment table and the runtime assignment table have been updated. The other chapters have not been updated yet.

1. Article purpose

The purpose of this article is to:

• briefly introduce the I3C peripheral and its main features,
• indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
• list the software frameworks and drivers managing the peripheral,
• explain how to configure the peripheral.

2. Peripheral overview

The I3C peripheral is used to handle communication between this device and others, such as sensors and host processors connected on an I3C bus.
An I3C bus is a two-wire, serial single-ended, multidrop bus, intended to improve a legacy I²C bus.
This I3C peripheral is SDR-only (single data rate) and implements all the features required by the MIPI^® I3C specification v1.1.
It can control all I3C bus-specific sequencing, protocol, arbitration, and timing, and can act as controller (formerly known as master), or as target (formerly known as slave).
When acting as controller, the I3C peripheral improves the features on the I²C interface preserving some backward compatibility: it allows an I²C target to operate on an I3C bus in legacy I²C fast mode (Fm) or legacy I²C fast mode plus (Fm+), provided that the latter does not perform clock stretching.

For more information about I3C, refer to this link: MIPI^® I3C Wikipedia page or MIPI^® I3C.

Here are the main features:

• MIPI^® I3C specification v1.1, as:
  • I3C SDR-only primary controller
  • I3C SDR-only secondary controller
  • I3C SDR-only target
• I3C SCL bus clock frequency up to 12.5 MHz
• Messages:
  • Legacy I²C read/write messages to legacy I²C targets in Fm/Fm+
  • I3C SDR read/write private messages
  • I3C SDR broadcast CCC messages
  • I3C SDR read/write direct CCC messages

Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.

3. Peripheral usage

This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm^® Cortex^®-A processor, and the STM32CubeMPU Package running on the Arm^® Cortex^®-M processor.

3.1. Boot time assignment

3.1.1. On STM32MP21x lines 

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given boot time context.
• ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
		Instance	Cortex-A35 secure (ROM code)	Cortex-A35 secure (TF-A BL2)	Cortex-A35 nonsecure (U-Boot)
Low speed interface	I3C	I3C1		⬚	☐
		I3C2		⬚	☐
		I3C3		⬚	☐

3.1.2. On STM32MP23x lines 

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given boot time context.
• ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
		Instance	Cortex-A35 secure (ROM code)	Cortex-A35 secure (TF-A BL2)	Cortex-A35 nonsecure (U-Boot)
Low speed interface	I3C	I3C1		⬚	☐
		I3C2		⬚	☐
		I3C4		⬚	☐

3.1.3. On STM32MP25x lines 

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given boot time context.
• ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
		Instance	Cortex-A35 secure (ROM code)	Cortex-A35 secure (TF-A BL2)	Cortex-A35 nonsecure (U-Boot)
Low speed interface	I3C	I3C1		⬚	☐
		I3C2		⬚	☐
		I3C3		⬚	☐
		I3C4		⬚	☐

3.2. Runtime assignment

3.2.1. On STM32MP21x lines 

Click on to expand or collapse the legend...

STM32MP21 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given runtime context.
• ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP21 reference manuals.

Domain	Peripheral	Runtime allocation					Comment
		Instance	Cortex-A35 secure (OP-TEE / TF-A BL31)	Cortex-A35 nonsecure (Linux)	Cortex-M33 secure (TF-M)	Cortex-M33 nonsecure (STM32Cube)
Low speed interface	I3C	I3C1	⬚OP-TEE ⬚TF-A BL31	☐	⬚	☐
		I3C2	⬚OP-TEE ⬚TF-A BL31	☐	⬚	☐
		I3C3	⬚OP-TEE ⬚TF-A BL31	☐	⬚	☐

3.2.2. On STM32MP23x lines 

Click on to expand or collapse the legend...

STM32MP23 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given runtime context.
• ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP23 reference manuals.

Domain	Peripheral	Runtime allocation					Comment
		Instance	Cortex-A35 secure (OP-TEE / TF-A BL31)	Cortex-A35 nonsecure (Linux)	Cortex-M33 secure (TF-M)	Cortex-M33 nonsecure (STM32Cube)
Low speed interface	I3C	I3C1	⬚OP-TEE ⬚TF-A BL31	☐	⬚	☐
		I3C2	⬚OP-TEE ⬚TF-A BL31	☐	⬚	☐
		I3C4	⬚OP-TEE ⬚TF-A BL31	☐	⬚	☐

3.2.3. On STM32MP25x lines 

Click on to expand or collapse the legend...

STM32MP25 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given runtime context.
• ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.

Domain	Peripheral	Runtime allocation						Comment
		Instance	Cortex-A35 secure (OP-TEE / TF-A BL31)	Cortex-A35 nonsecure (Linux)	Cortex-M33 secure (TF-M)	Cortex-M33 nonsecure (STM32Cube)	Cortex-M0+ (STM32Cube)
Low speed interface	I3C	I3C1	⬚OP-TEE ⬚TF-A BL31	☐	⬚	☐
		I3C2	⬚OP-TEE ⬚TF-A BL31	☐	⬚	☐
		I3C3	⬚OP-TEE ⬚TF-A BL31	☐	⬚	☐
		I3C4	⬚OP-TEE ⬚TF-A BL31	☐	⬚	☐	☐

4. Software frameworks and drivers

Below are listed the software frameworks and drivers managing the I3C peripheral for the embedded software components listed in the above tables.

• Linux^®: I3C SDR-only primary controller as defined in MIPI^® I3C specification v1.1 in I3C driver using I3C framework
• STM32Cube: I3C HAL driver and header file of I3C HAL module

5. How to assign and configure the peripheral

The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral by generating:

• partial device trees (pin control and clock tree) for the OpenSTLinux software components,
• HAL initialization code for the STM32CubeMPU Package.

The configuration is applied by the firmware running in the context in which the peripheral is assigned.

Mobile Industry Processor Interface, open membership organization that includes leading companies in the mobile industry that share the objective of defining and promoting open specifications for interfaces inside mobile terminals, see MIPI^® Alliance standard web site https://www.mipi.org

Serial clock line

Board support package

Arm^® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Cortex^®

Read only memory

Trusted firmware for Arm^® Cortex^®-A

Boot loader stage 2

Das U-Boot -- the universal boot loader (see U-Boot)

Open portable trusted execution environment

Linux^® is a registered trademark of Linus Torvalds.

Hardware abstraction layer

Mobile Industry Processor Interface, open membership organization that includes leading companies in the mobile industry that share the objective of defining and promoting open specifications for interfaces inside mobile terminals, see MIPI^® Alliance standard web site https://www.mipi.org

Serial clock line

Board support package

Arm^® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Cortex^®

Read only memory

Trusted firmware for Arm^® Cortex^®-A

Boot loader stage 2

Das U-Boot -- the universal boot loader (see U-Boot)

Open portable trusted execution environment

Linux^® is a registered trademark of Linus Torvalds.

Hardware abstraction layer