1. Article purpose[edit source]
The purpose of this article is to:
- briefly introduce the I3C peripheral and its main features,
- indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
- list the software frameworks and drivers managing the peripheral,
- explain how to configure the peripheral.
2. Peripheral overview[edit source]
The I3C peripheral is used to handle communication between this device and others, such as sensors and host processor, connected on an I3C bus.
An I3C bus is a two-wire, serial single-ended, multidrop bus, intended to improve a legacy I2C bus.
This I3C peripheral is SDR-only (Single Data Rate) and implements all the features required by the MIPI® I3C specification v1.1.
It can control all I3C bus-specific sequencing, protocol, arbitration, and timing, and can act as controller (formerly known as master), or as target (formerly known as slave).
When acting as controller, the I3C peripheral improves the features on the I2C interface preserving some backward compatibility: it allows an I2C target to operate on an I3C bus in legacy I2C fast-mode (Fm) or legacy I2C fast-mode plus (Fm+), provided that the latter does not perform clock stretching.
For more information about I3C, please refer to this link: MIPI® I3C Wikipedia page [1] or MIPI® I3C[2]
Here are the main features:
- MIPI® I3C specification v1.1, as:
- I3C SDR-only primary controller
- I3C SDR-only secondary controller
- I3C SDR-only target
- I3C SCL bus clock frequency up to 12.5 Mhz
- Messages:
- Legacy I2C read/write messages to legacy I2C targets in Fm/Fm+
- I3C SDR read/write private messages
- I3C SDR broadcast CCC messages
- I3C SDR read/write direct CCC messages
Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.
3. Peripheral usage[edit source]
This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm® Cortex®-A processor(s), and the STM32CubeMPU Package running on the Arm® Cortex®-M processor.
3.1. Boot time assignment[edit source]
3.1.1. On STM32MP2 series[edit source]
Click on 
to expand or collapse the legend...
- ☐ means that the peripheral can be assigned to the given boot time context.
- ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
- ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.
| Domain | Peripheral | Boot time allocation | Comment
| |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 non-secure (U-Boot) | |||
| Low speed interface | I3C | I3C1 | ⬚ | ☐ | ||
| I3C2 | ⬚ | ☐ | ||||
| I3C3 | ⬚ | ☐ | ||||
| I3C4 | ⬚ | ☐ | ||||
3.2. Runtime assignment[edit source]
3.2.1. On STM32MP25x lines 
[edit source]
Click on to expand or collapse the legend...
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ☐ means that the peripheral can be assigned to the given runtime context.
- ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment
| |||||
|---|---|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 non-secure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 non-secure (STM32Cube) |
Cortex-M0+ (STM32Cube) | |||
| Low speed interface | I3C | I3C1 | ⬚OP-TEE ⬚TF-A BL31 |
☐ | ⬚ | ☐ | ||
| I3C2 | ⬚OP-TEE ⬚TF-A BL31 |
☐ | ⬚ | ☐ | ||||
| I3C3 | ⬚OP-TEE ⬚TF-A BL31 |
☐ | ⬚ | ☐ | ||||
| I3C4 | ⬚OP-TEE ⬚TF-A BL31 |
☐ | ⬚ | ☐ | ☐ | |||
4. Software frameworks and drivers[edit source]
Below are listed the software frameworks and drivers managing the I3C peripheral for the embedded software components listed in the above tables.
- Linux®: I3C SDR-only primary controller as defined in MIPI® I3C specification v1.1 in I3C driver
- STM32Cube: I3C HAL driver and header file of I3C HAL module
5. How to assign and configure the peripheral[edit source]
The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral by generating:
- partial device trees (pin control and clock tree) for the OpenSTLinux software components,
- HAL initialization code for the STM32CubeMPU Package.
The configuration is applied by the firmware running in the context in which the peripheral is assigned.
6. References[edit source]
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.