1. Article purpose[edit | edit source]
The STM32MP15xx device errata sheet[1] lists the different device limitations and explains the corresponding workarounds (software and/or hardware) if any.
The objective of this article is to explain which of the workarounds, described in this errata sheet, are applicable and implemented in ecosystem release v4.1.0 .
This article lists
- errata to be workaround by the customers,
- errata workaround implemented in STM32MPU Ecosystem releases,
- and errata not applicable in STM32MPU Ecosystem releases.
Errata, present in STM32MP15xx device errata sheet[1] and not listed in this article, have no workaround implemented in STM32MPU Ecosystem releases.
2. Legend[edit | edit source]
The section column refers to the number of the erratum chapter in the errata sheet document.
Rev.Y columns , present in the tables below, refer to the availability and status of a given errata workaround for the described erratum in errata sheet document:
- A = workaround available
- P = partial workaround available
- N = no workaround available
OpenSTLinux and CubeMP1 columns , present in the tables below, refer to the availability of a workaround for a given STM32MP13 ecosystem release:
- U = workaround to implement by User
- I = workaround Implemented
- NA= Errata Not Applicable in ST software release
Wave your mouse over a status in the table to display the corresponding legend.
3. Workarounds to implement by customer[edit | edit source]
| Function | Section | Limitation | Rev.Z | 
|
|
Comment |
|---|---|---|---|---|---|---|
| Arm® Cortex®-A7 core | 2.1.1 | Memory locations might be accessed speculatively due to instruction fetches when HCR.VM is set | A | U | NA | OpenSTLinux distribution does not activate Arm® Cortex®-A7 Hypervisor mode and hence the Virtual Memory second stage of translation. The customer should implement the workaround if the Hypervisor mode is used in his/her product. |
| Arm® Cortex®-M4 core | 2.2.1 | Interrupted loads to SP can cause erroneous behavior | A | NA | U | STM32CubeMP15_Package: Limitation only on hand-written assembly code. The customer should implement the workaround in the product assembly code. |
| 2.2.2 | VDIV or VSQRT instructions might not complete correctly when very short ISRs are used | A | NA | U | STM32CubeMP15_Package provided as example. The customer should implement the workarounds according to the user code and product configuration. | |
| 2.2.3 | Store immediate overlapping exception return operation might vector to incorrect interrupt | A | NA | U | STM32CubeMP15_Package: Minor impact on the system. The customer should implement the workaround according to the MPU configuration. | |
| System | 2.3.22 | Improper isolation of protected secure resources | P | U | OpenSTLinux distribution: Errata and workaround described in Security advisory TN1500. | |
| 2.3.23 | Improper MCU resource isolations | A | U | OpenSTLinux distribution: The customer should implement the workaround. | ||
| DDRPHYC | 2.4.2 | DDR_CLK jitter out of JEDEC requirement for 32-bit LPDDR2/LPDDR3 at low device Tj | A | U | U | ST boards use DDR3 instead of LPDDR2/3. The customer should implement the workaround if he uses LPDDR2/3 in his board design. |
| 2.4.3 | Data corruption at low device Tj combined with low 32-bit LPDDR2/LPDDR3 I/O supply voltage | A | U | U | ST boards use DDR3 instead of LPDDR2/3. The customer should implement the workaround if he uses LPDDR2/3 in his board design. | |
| DMAMUX | 2.7.4 | Wrong input DMA request routed upon specific DMAMUX_CxCR register write coinciding with synchronization event | A | NA | U | STM32CubeMP15_Package: The customer should provide the right DMAMUX signal polarity configuration when calling the HAL_DMAEx_ConfigMuxSync() function provided in STM32CubeMP15_Package Src/stm32mp1xx_hal_dma_ex.c . |
| FMC | 2.8.1 | NOR Flash memory/PSRAM incorrect bus turnaround timing | A | U | OpenSTLinux distribution: Delays to applied by customer device tree. | |
| ADC | 2.11.4 | ADC_AWDy_OUT reset by non-guarded channels | A | U | U | OpenSTLinux distribution: The customer should implement this workaround by configuring only ADC channels that are guarded by a watchdog in the device tree.
STM32CubeMP15_Package: The customer should implement this workaround by configuring only ADC channels that are guarded by a watchdog in the application. |
| 2.11.7 | ADC ANA0/ANA1 resolution limited when Gigabit Ethernet is used | P | U | U | OpenSTLinux distribution: The customer should implement this workaround by limiting the ADC data resolution in the device tree
STM32CubeMP15_Package: The customer should implement this workaround by limiting the ADC data resolution in the application. | |
| 2.11.8 | ADC missing codes in differential 16-bit static acquisition | P | U | U | OpenSTLinux distribution: The customer should implement this workaround by configuring only ADC channels that are guarded by a watchdog in the device tree
STM32CubeMP15_Package: The customer should implement this workaround by configuring only ADC channels that are guarded by a watchdog in the application. | |
| DAC | 2.13.1 | Invalid DAC channel analog output if the DAC channel MODE bitfield is programmed before DAC initialization | A | NA | U | STM32CubeMP15_Package: Both Normal and Sample and hold modes are supported by the HAL drivers. The user should call properly HAL_DAC_Init before HAL_DAC_ConfigChannel to avoid the issue. |
| LPTIM | 2.18.1 | Device may remain stuck in LPTIM interrupt when entering Stop mode | A | NA | U | OpenSTLinux distribution: The LPTIM interrupt is not used.
STM32CubeMP15_Package: The customer should implement this workaround in MspDeinit(). |
| I2C | 2.20.2 | Spurious bus error detection in master mode | A | U | U | OpenSTLinux distribution: The LPTIM interrupt is not used.
STM32CubeMP15_Package: Issue visible only in interrupt mode, not in DMA mode. Bus Error should be handled by a Timeout at application level.). |
4. Workarounds implemented in STM32MP15 ecosystem releases[edit | edit source]
| Function | Section | Limitation | Rev.Z |
|
|
Comment |
|---|---|---|---|---|---|---|
| Arm® Cortex®-A7 core | 2.1.2 | Cache maintenance by set/way operations can execute out of order | A | I | NA | OpenSTLinux distribution: Implementation accepted by the community since Linux® kernel v5.3 in arch/arm/Kconfig (refer to ARM_ERRATA_814220). |
| System | 2.3.3 | HSE external oscillator required in some LTDC use cases | P | I | OpenSTLinux distribution: Implemented in device tree.
Hardware implementation of the external oscillator connected to the HSE pins available on STM32MP157x-EV1 MB1263 Rev.C (aka "MB1263C") and STM32MP157x-DKx MB1272 Rev.C (aka "MB1272C"). | |
| 2.3.4 | RCC cannot exit Stop and Low-power Stop modes | A | I | |||
| 2.3.5 | Incorrect reset of glitch-free kernel clock switch | P | I | OpenSTLinux distribution: By default, STPMIC1 performs a VDDCORE reset on NRST activation. | ||
| 2.3.6 | Limitation of aclk/hclk5/hclk6 to 200 MHz when used as SDMMC1/2 kernel clock | P | I | OpenSTLinux distribution: Implemented in device tree with a clock tree that uses a SDMMC1/SDMMC2 kernel clock source different from the aclk/hclk5/hclk6 bus clock. | ||
| 2.3.9 | Cortex-M4 cannot use I/O compensation on Standby mode exit | A | NA | I | OpenSTLinux distribution: The examples delivered with STM32Cube use only IOSPEEDR[1:0] settings 00 and 01. | |
| QUADSPI | 2.9.1 | Memory-mapped read of last memory byte fails | P | I | ||
| VREFBUF | 2.14.2 | Overshoot on VREFBUF output | A | I | ||
| DTS | 2.12.1 | DTS incorrect operation with LSE as reference clock and PCLK enabled | P | I | ||
| LPTIM | 2.18.2 | MCU may remain stuck in LPTIM interrupt when clearing event flag | P | NA | I | |
| RTC and TAMP | 2.19.2 | Calendar initialization may fail in case of consecutive INIT mode entry | A | I | ||
| I2C | 2.20.1 | Wrong data sampling when data setup time (tSU;DAT) is shorter than one I2C kernel clock period | P | I | I | OpenSTLinux distribution: Workaround implemented in device tree with a clock tree that configures the I2C kernel clock source to a frequency higher than 20 MHz. |
| SPI | 2.22.1 | Master data transfer stall at system clock much faster than SCK | A | I | I | OpenSTLinux distribution: SPI is disabled after each EOT
STM32CubeMP15_Package: SPI is disabled after each EOT. |
| 2.22.3 | TXP interrupt occurring while SPI disabled | A | I | I | OpenSTLinux distribution: all interrupts are disabled before the SPI is disabled. | |
| ETH | 2.25.2 | Rx DMA may fail to recover upon DMA restart following a bus error, with Rx timestamping enabled | A | I | OpenSTLinux distribution: Workaround is implemented in stmmac driver. When a bus error is detected, a SW reset is done and all the descriptors are cleared (Rx and Tx), the queues and descriptors are reinitialized | |
| 2.25.6 | ARP offload function not effective | A | I | |||
| 2.25.10 | DMA spurious state upon AXI DMA slave bus error | P | I | OpenSTLinux distribution: Workaround is implemented is stmmac driver |
5. Workarounds not applicable in STM32MP15 ecosystem releases[edit | edit source]
| Function | Section | Limitation | Rev.Z |
|
|
Comment |
|---|---|---|---|---|---|---|
| System | 2.3.19 | DLYB limits SDMMC throughput | N | NA | OpenSTLinux distribution: Errata impacts only HS200 abd SDR104 modes which are not enabled in OpenSTLinux distribution. A warning can be found on this topic on SDMMC device tree configuration. | |
| 2.3.21 | Wrong value in Coresight M4 ROM table | A | NA | NA | STM32CubeMP15_Package: DeviceID not used. All the examples provided are compiled for MP15. | |
| DMAMUX | 2.7.1 | SOFx not asserted when writing into DMAMUX_CFR register | N | NA | OpenSTLinux distribution: DMA synchronization event is not used. | |
| 2.7.2 | OFx not asserted for trigger event coinciding with last DMAMUX request | N | NA | OpenSTLinux distribution: DMA Trigger event is not used. | ||
| 2.7.3 | OFx not asserted when writing into DMAMUX_RGCFR register | N | NA | OpenSTLinux distribution: DMA Trigger event is not used. | ||
| 2.7.4 | Wrong input DMA request routed upon specific DMAMUX_CxCR register write coinciding with synchronization event | A | NA | U | OpenSTLinux distribution: DMA synchronization event is not used. | |
| FMC | 2.8.2 | Incorrect FMC_CLK clock period when CLKDIV value is changed on-the-fly in continuous clock mode | A | NA | OpenSTLinux distribution: CLKDIV can't be changed on-the-fly. | |
| 2.8.3 | NAND Flash memory IREF/IFEF flags wrongly asserted just after enabling in FMC_IER | A | NA | OpenSTLinux distribution: IREF/IFEF flags are not used. | ||
| 2.8.4 | Command sequencer accesses NAND Flash memory device while PBKEN bit is cleared in FMC_PCR | A | NA | OpenSTLinux distribution: PBKEN bit is set at probe time and never cleared on the flag. | ||
| 2.8.5 | NAND Flash memory IREF flag wrongly asserted after reset | A | NA | |||
| SDMMC | 2.10.1 | End-of-buffer status flag not cleared when the last burst data is delayed by the slave | A | NA | OpenSTLinux distribution: Not applicable in OpenSTLinux, as IDMABTC status flag is not used in our driver. | |
| 2.10.2 | The first word of the transfer following a linked list error may be wrong | A | NA | OpenSTLinux distribution: Not applicable in OpenSTLinux, as the linked list is built and ready before starting the data transfer (ABR bit always set to 1) | ||
| 2.10.3 | Command response and receive data end bits not checked | N | NA | NA | Not an issue from SW side as not visible by the SW. | |
| ADC | 2.11.1 | New context conversion initiated without waiting for trigger when writing new context in ADC_JSQR with JQDIS = 0 and JQM = 0 | A | NA | OpenSTLinux distribution: JQDIS = 1, this issue occurs only when JQDIS = 0. | |
| 2.11.2 | Two consecutive context conversions fail when writing new context in ADC_JSQR just after previous context completion with JQDIS = 0 and JQM = 0 | A | NA | OpenSTLinux distribution: JQDIS = 1, this issue occurs only when JQDIS = 0. | ||
| 2.11.3 | Unexpected regular conversion when two consecutive injected conversions are performed in Dual interleaved mode | A | NA | OpenSTLinux distribution: Dual mode is not implemented. | ||
| 2.11.5 | Injected data stored in the wrong ADC_JDRx registers | A | NA | OpenSTLinux distribution: Injected conversion not implemented. | ||
| 2.11.6 | ADC slave data may be shifted in Dual regular simultaneous mode | A | NA | OpenSTLinux distribution: Dual mode is not implemented. | ||
| DAC | 2.13.1 | Invalid DAC channel analog output if the DAC channel MODE bitfield is programmed before DAC initialization | A | NA | U | OpenSTLinux distribution:The Linux DAC driver uses only the Normal mode. It never needs to modify the MODE bitfield. |
| LPTIM | 2.18.1 | Device may remain stuck in LPTIM interrupt when entering Stop mode | A | NA | U | OpenSTLinux distribution: LPTIM interrupt is not used |
| 2.18.2 | MCU may remain stuck in LPTIM interrupt when clearing event flag | P | NA | I | OpenSTLinux distribution: LPTIM interrupt is not used | |
| RTC and TAMP | 2.19.5 | REFCKON write protection associated to INIT KEY instead of CAL KEY | A | NA | OpenSTLinux distribution: REFCKON is not implemented in linux driver | |
| I2C | 2.20.3 | Spurious master transfer upon own slave address match | P | NA | STM32CubeMP15_Package: The multimaster mode implementation of I2C HAL driver prevents such case from happening. | |
| 2.20.5 | Transmission stalled after first byte transfer | P | NA | OpenSTLinux distribution: Condition never reached in Linux OS thanks to the specific implementation (TXDR always filled before transmission). | ||
| USART | 2.21.1 | Anticipated end-of-transmission signaling in SPI slave mode | A | NA | OpenSTLinux distribution: SPI slave mode is not implemented | |
| 2.21.3 | Received data may be corrupted upon clearing the ABREN bit | A | NA | OpenSTLinux distribution: Condition never reached in Linux OS thanks to the specific implementation (ABREN bit never cleaned up in USART_CR2 register). | ||
| 2.21.4 | Noise error flag set while ONEBIT is set | N | NA | OpenSTLinux distribution: Not applicable as Linux Framework doesn't handle the Noise error indication. | ||
| SPI | 2.22.2 | Corrupted CRC return at non-zero UDRDET setting | P | NA | OpenSTLinux distribution: CRC is not supported | |
| 2.22.4 | Possible corruption of last-received data depending on CRCSIZE setting | A | NA | OpenSTLinux distribution: CRC is not supported | ||
| ETH | 2.25.3 | Spurious receive watchdog timeout interrupt | A | NA | OpenSTLinux distribution: This bug does not affect OpenSTLinux because of the specific implementation of the driver. | |
| 2.25.11 | Incorrect DMA transfer state in TEB[2:0] and REB[2:0] on bus error | A | NA | OpenSTLinux distribution: No functional impact because only the DMA transfer state is incorrect. | ||
| 2.25.13 | Fatal bus error interrupt not generated when the descriptor posted write is enabled | A | NA | OpenSTLinux distribution: No impact as the register DSPW bit if the ETH_DMAMR register is never used in dwmac driver. It remains set to 0 in any condition. |
6. References[edit | edit source]
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.