1. Article purpose
The purpose of this article is to:
- briefly introduce the OCTOSPI I/O manager peripheral and its main features,
- indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
- list the software frameworks and drivers managing the peripheral,
- explain how to configure the peripheral.
2. Peripheral overview
The OCTOSPI I/O manager peripheral is a low-level interface that enables an efficient OCTOSPI pin assignment with a full I/O matrix (before alternate function map), and multiplex of single/dual/quad/octal SPI interfaces over the same bus.
Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.
3. Peripheral usage
This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm® Cortex®-A processor(s), and the STM32CubeMPU Package running on the Arm® Cortex®-M processor.
3.1. Boot time assignment
3.1.1. On STM32MP23x lines 
Click on 
to expand or collapse the legend...
| Domain | Peripheral | Boot time allocation | Comment
| |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | |||
| Mass storage | OCTOSPIM | OCTOSPIM | ☐ | ☐ | ☐ | TF-A BL2 relies on OCTOSPIM configuration applied by ROM code |
3.1.2. On STM32MP25x lines
Click on to expand or collapse the legend...
| Domain | Peripheral | Boot time allocation | Comment
| |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | |||
| Mass storage | OCTOSPIM | OCTOSPIM | ☐ | ☐ | ☐ | TF-A BL2 relies on OCTOSPIM configuration applied by ROM code |
3.2. Runtime assignment
3.2.1. On STM32MP23x lines
Click on to expand or collapse the legend...
| Domain | Peripheral | Runtime allocation | Comment
| ||||
|---|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | |||
| Mass storage | OCTOSPIM | OCTOSPIM | ☐OP-TEE | ☐ | ☐ | ☐ | |
3.2.2. On STM32MP25x lines
Click on to expand or collapse the legend...
| Domain | Peripheral | Runtime allocation | Comment
| |||||
|---|---|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) |
Cortex-M0+ (STM32Cube) | |||
| Mass storage | OCTOSPIM | OCTOSPIM | ☐OP-TEE | ☐ | ☐ | ☐ | ||
4. Software frameworks and drivers
Below are listed the software frameworks and drivers managing the OCTOSPI I/O manager peripheral for the embedded software components listed in the above tables.
- Linux®: driver (drivers/misc/stm32_omm.c )
- STM32Cube: header file of OCTOSPI HAL module
- U-Boot: driver (drivers/misc/stm32_omm.c )
- OP-TEE: driver (core/drivers/stm32_omm.c )
5. How to assign and configure the peripheral
The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral by generating:
- partial device trees (pin control and clock tree) for the OpenSTLinux software components,
- HAL initialization code for the STM32CubeMPU Package.
The configuration is applied by the firmware running in the context in which the peripheral is assigned.
For Linux kernel configuration, refer to OCTOSPIM device tree configuration.
6. References