Last edited 6 months ago

STM32MP15 peripherals overview

Applicable for STM32MP15x lines

This article lists all internal peripherals embedded in STM32MP15x lines More info.png and shows the assignment possibilities to the execution contexts for each one of them.
From this article, you can also access to individual peripheral articles in which information related to the overview and configuration can be found.

1. Internal peripherals overview[edit source]

The figure below shows all peripherals embedded in STM32MP15x lines More info.png, grouped per functional domains that are reused in many places of this wiki to structure the articles.

Several execution contexts exist on STM32MP15x lines More info.png[1], corresponding to the different Arm cores and associated security modes:

  •  Arm dual core Cortex-A7 secure  (Trustzone), running ROM code and TF-A BL2 at boot time, and running OP-TEE at runtime
  •  Arm dual core Cortex-A7 non secure , running U-Boot at boot time, and running Linux at runtime
  •  Arm Cortex-M4 non-secure , running STM32Cube


Some peripherals can be strictly assigned to one execution context: this is the case for most of the peripherals, like USART or I2C.
Other ones can be shared between several execution contexts: this is the case for system peripherals, like PWR or RCC.
The legend below shows how assigned and shared peripherals are identified in the assignment diagram that follows:

STM32MP1IPsOverview legend.png

Both the diagram below and the following summary table (in Internal peripherals runtime assignment and Internal peripherals boot time assignment chapters below) are clickable in order to jump to each peripheral overview articles and get more detailed information (like software frameworks used to control them). They list STMicroelectronics recommendations. The STM32MP15 reference manual [2] may expose more possibilities than what is shown here.


Cortex-A7Cortex-M4STGENSYSCFGRTCEXTIGICNVICIWDGIWDGWWDGDMADMADMAMUXMDMASYSRAMDDR via DDR CTRLBKPSRAMMCU SRAMMCU SRAMRETRAMTIMTIMLPTIMGPIOGPIOIPCCHSEMRCCPWRDTSDDRPERFMDBGMCUHDPBSECQUADSPIFMCSDMMCFDCANETHSDMMCUSBHOTGUSBPHYCUSARTUSARTUSARTI2CI2CI2CSPISPIRNGHASHETZPCCRYPCRCTZCRNGHASHTAMPCRYPCRCGPUDSILTDCDCMICECVREFBUFDACDFSDMADCSPI I2SSPDIFRXSAI
STM32MP1 internal peripherals overview

2. Internal peripherals runtime assignment[edit source]

Click on How to.png to expand or collapse the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned to the given runtime context.
  • means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
  • means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain Peripheral Runtime allocation Comment How to.png
Instance Cortex-A7
secure
(OP-TEE)
Cortex-A7
non-secure
(Linux)
Cortex-M4

(STM32Cube)
Analog ADC ADC Assignment (single choice)
Analog DAC DAC Assignment (single choice)
Analog DFSDM DFSDM Assignment (single choice)
Analog VREFBUF VREFBUF Assignment (single choice)
Audio SAI SAI1 Assignment (single choice)
SAI2 Assignment (single choice)
SAI3 Assignment (single choice)
SAI4 Assignment (single choice)
Audio SPDIFRX SPDIFRX Assignment (single choice)
Coprocessor IPCC IPCC Shared (none or both)
Coprocessor HSEM HSEM
Core RTC RTC RTC is mandatory to resynchronize STGEN after exiting low-power modes.
Core STGEN STGEN
Core SYSCFG SYSCFG
Core/DMA DMA DMA1 Assignment (single choice)
DMA2 Assignment (single choice)
Core/DMA DMAMUX DMAMUX Shareable (multiple choices supported)
Core/DMA MDMA MDMA Shareable (multiple choices supported)
Core/Interrupts EXTI EXTI Shared
Core/Interrupts GIC GIC
Core/Interrupts NVIC NVIC
Core/IOs GPIO GPIOA-K (*) The pins can individually be shared

(*): despite they cannot be secured, the pins can be used by the secure context

GPIOZ The pins can individually be secured or shared
Core/RAM BKPSRAM BKPSRAM Assignment (single choice)
Core/RAM DDRCTRL DDR
Core/RAM MCU SRAM SRAM1 Assignment (between A7 S and A7 NS / M4)
Shareable (between A7 NS and M4)
SRAM2 Assignment (between A7 S and A7 NS / M4)
Shareable (between A7 NS and M4)
SRAM3 Assignment (between A7 S and A7 NS / M4)
Shareable (between A7 NS and M4)
SRAM4 Assignment (between A7 S and A7 NS / M4)
Shareable (between A7 NS and M4)
Core/RAM RETRAM RETRAM Assignment to the Arm® Cortex®-M4 if used
Core/RAM SYSRAM SYSRAM Shareable (multiple choices supported)

Secure section required for low power entry and exit

Core/Timers LPTIM LPTIMx (x = 1 to 5) Assignment (single choice)
Core/Timers TIM TIM1 (APB2 group) Assignment (single choice)
TIM2 (APB1 group) Assignment (single choice)
TIM3 (APB1 group) Assignment (single choice)
TIM4 (APB1 group) Assignment (single choice)
TIM5 (APB1 group) Assignment (single choice)
TIM6 (APB1 group) Assignment (single choice)
TIM7 (APB1 group) Assignment (single choice)
TIM8 (APB2 group) Assignment (single choice)
TIM12 (APB1 group) Assignment (single choice)
TIM12 or TIM15 can be used for HSI/CSI calibration[3]
TIM13 (APB1 group) Assignment (single choice)
TIM14 (APB1 group) Assignment (single choice)
TIM15 (APB2 group) Assignment (single choice)
TIM12 or TIM15 can be used for HSI/CSI calibration[3]
TIM16 (APB2 group) Assignment (single choice)
TIM17 (APB2 group) Assignment (single choice)
Core/Watchdog IWDG IWDG1
IWDG2 Shared (none or both):
  • Cortex-A7 non secure for reload
  • Cortex-A7 secure for early interrupt handling
Core/Watchdog WWDG WWDG
High speed interface OTG (USB OTG) OTG (USB OTG)
High speed interface USBH (USB Host) USBH (USB Host)
High speed interface USBPHYC (USB HS PHY controller) USBPHYC (USB HS PHY controller)
Low speed interface I2C I2C1 Assignment (single choice)
I2C2 Assignment (single choice)
I2C3 Assignment (single choice)
I2C4 Assignment (single choice).
Used for PMIC control on ST boards.
I2C5 Assignment (single choice)
I2C6 Assignment (single choice)
Low speed interface
or
audio
SPI SPI2S1 Assignment (single choice)
SPI2S2 Assignment (single choice)
SPI2S3 Assignment (single choice)
SPI4 Assignment (single choice)
SPI5 Assignment (single choice)
SPI6 Assignment (single choice)
Low speed interface USART USART1 Assignment (single choice)
USART2 Assignment (single choice)
USART3 Assignment (single choice)
UART4 Assignment (single choice).
Used for Linux® serial console on ST boards.
UART5 Assignment (single choice)
USART6 Assignment (single choice)
UART7 Assignment (single choice)
UART8 Assignment (single choice)
Mass storage FMC FMC Assignment (single choice)
Mass storage QUADSPI QUADSPI Assignment (single choice)
Mass storage SDMMC SDMMC1
SDMMC2
SDMMC3 Assignment (single choice)
Networking ETH ETH Assignment (single choice)
Networking FDCAN FDCAN1 Assignment (single choice)
FDCAN2 Assignment (single choice)
Power & Thermal DTS DTS
Power & Thermal PWR PWR
Power & Thermal RCC RCC
Security BSEC BSEC Cortex-M4 can read BSEC shadow register (BSEC_OTP_DATAx) to read a lower OTP value
Security CRC CRC1
CRC2
Security CRYP CRYP1 Assignment (single choice)
CRYP2
Security ETZPC ETZPC
Security HASH HASH1 Assignment (single choice)
HASH2
Security RNG RNG1 Assignment (single choice)
RNG2
Security TZC TZC
Security TAMP TAMP
Trace & Debug DBGMCU DBGMCU
Trace & Debug DDRPERFM DDRPERFM
Trace & Debug HDP HDP
Visual CEC CEC Assignment (single choice)
Visual DCMI DCMI Assignment (single choice)
Visual DSI DSI
Visual GPU GPU
Visual LTDC LTDC

3. Internal peripherals boot time assignment[edit source]

Click on How to.png to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

  • means that the peripheral can be assigned to the given boot time context.
  • means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
  • means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
  • is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain Peripheral Boot time allocation Comment How to.png
Instance Cortex-A7
secure
(ROM code)
Cortex-A7
secure
(TF-A BL2)
Cortex-A7
non-secure
(U-Boot)
Analog ADC ADC
Coprocessor HSEM HSEM
Core RTC RTC
Core STGEN STGEN
Core SYSCFG SYSCFG
Core/IOs GPIO GPIOA-K (*) The pins cannot be secured

(*): despite they cannot be secured, the pins can be used by the secure context

GPIOZ The pins can individually be secured
Core/RAM BKPSRAM BKPSRAM
Core/RAM DDRCTRL DDR
Core/RAM MCU SRAM Any instance
Core/RAM RETRAM RETRAM
Core/RAM SYSRAM SYSRAM
Core/Timers LPTIM LPTIMx (x = 1 to 5) LPTIM are not used at boot time.
Core/Timers TIM TIMx (x = 2 to 7, 12, 13, 14. APB1 group)
TIMx (x = 1, 8, 15, 16, 17. APB2 group)
Core/Watchdog IWDG Any instance
High speed interface OTG (USB OTG) OTG (USB OTG) The OTG can be used by ROM code, FSBL and SSBL in DFU mode to support serial boot.
It can be used also in U-boot with command line tools.
High speed interface USBH (USB Host) USBH (USB Host)
High speed interface USBPHYC (USB HS PHY controller) USBPHYC (USB HS PHY controller) The USBPHYC can be used by ROM code, FSBL and SSBL in DFU mode to support serial boot.
It can be used also in U-boot by OTG and USBH with command line tools.
Low speed interface I2C Any instance
Low speed interface USART Any instance
Mass storage FMC FMC
Mass storage QUADSPI QUADSPI
Mass storage SDMMC SDMMC1
SDMMC2
Networking ETH Any instance Assignment (single choice)
Power & Thermal PWR PWR
Power & Thermal RCC RCC
Security BSEC BSEC
Security ETZPC Any instance ETZPC configuration is set by OP-TEE
Security HASH HASH1
HASH2 not used at boot time.
Security RNG RNG1
Security TZC TZC
Security TAMP TAMP
Trace & Debug DBGMCU DBGMCU
Visual DSI DSI
Visual LTDC LTDC

4. References[edit source]