STM32MP25 peripherals overview for M33-TD flavor

Applicable for

Trusted domain applicability

This article is only applicable to M33-TD flavor of STM32MP2 series

This article lists all internal peripherals embedded in STM32MP25x lines and shows the assignment possibilities to the execution contexts for each one of them.
From this article, you can also access to individual peripheral articles with information related to the overview and configuration aspects.

1. Internal peripherals overview[edit | edit source]

The figure below shows all peripherals embedded in STM32MP25x lines , grouped per functional domains that are reused in many places of this wiki to structure the articles.
Several execution contexts exist on STM32MP25x lines ^[1], corresponding to the different Arm cores and associated security modes:

Arm dual core Cortex-A35 secure (Trustzone), running ROM code and TF-A BL2 at boot time, and running OP-TEE and/or TF-A BL31 at runtime
Arm dual core Cortex-A35 non secure , running U-Boot at boot time, and running Linux at runtime
Arm Cortex-M33 secure (Trustzone), running TF-M
Arm Cortex-M33 non-secure , running STM32Cube
Arm Cortex-M0+, running HAL driver.

The legend below shows how assigned and shared peripherals are identified in the assignment diagram that follows:

When a peripheral box owns execution context color, that means the assignment of this peripheral is fixed by hardware to the execution context.
When a peripheral box owns a mix of two execution colors that means this peripheral is shared by hardware between the two execution contexts.
When a peripheral box has dark gray color, that means this peripheral is protected by RIF and could be assigned to any execution context.
When a peripheral box has light gray color, that means this peripheral is a RIF-aware peripheral. This peripheral owns several features which can be assigned independently to any execution context.

Internal peripheral assignment tables list assignment capabilities for each peripheral.

Both the diagram below and the following summary tables (in Internal peripherals runtime assignment and Internal peripherals boot time assignment chapters below) are clickable in order to jump to each peripheral overview articles and get more detailed information (like software frameworks used to control them). They list STMicroelectronics recommendations. The STM32MP25 reference manual ^[2] may expose more possibilities than what is shown here.

STM32MP25 internal peripherals overview

2. Internal peripherals boot time assignment[edit | edit source]

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by the OpenSTLinux BSP:

⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
☐ means that the peripheral can be assigned to the given boot time context.
☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

ADF internal peripheral

Domain	Peripheral	Boot time allocation					Comment
Domain	Peripheral	Instance	Cortex-A35 secure (ROM code)	Cortex-A35 secure (TF-A BL2)	Cortex-A35 nonsecure (U-Boot)	Cortex-M33 secure (MCUboot)	Comment
Core/Processors	Arm^® Cortex^®-A35	Arm^® Cortex^®-A35	✓	✓	✓	⬚	Can be started by MCUboot. Running the OpenSTLinux distribution.
Core/Processors	Arm^® Cortex^®-M33	Arm^® Cortex^®-M33				✓
Core/Processors	Arm^® Cortex^®-M0+ (coprocessor)	Arm^® Cortex^®-M0+		⬚	⬚
Analog	VREFBUF	VREFBUF			⬚		TF-M offers SCMI regulator service to manage VREFBUF
Analog	ADC	ADC12		⬚	☐	⬚
Analog	ADC	ADC3		⬚	☐	⬚
Analog	MDF	MDF1		⬚	⬚	⬚
Coprocessor	IPCC	IPCC1	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Coprocessor	IPCC	IPCC2	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core	STGEN	STGEN	✓	☑	Read-only ^(STGENR)
Core	RTC	RTC	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core/DMA	HPDMA	HPDMAx (x = 1 to 3)	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core/DMA	LPDMA	LPDMA1	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core/Interrupts	EXTI	EXTI1	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core/Interrupts	EXTI	EXTI2	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core/IOs	GPIO	GPIOA-K	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core/IOs	GPIO	GPIOZ	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core/RAM	SYSRAM	SYSRAM	✓	✓
Core/RAM	DDRCTRL & DDRPHYC	DDR				✓	Assignment is controlled by the RCC RIF 104 resource that also include the PLL2 control.
Core/RAM	SRAM	SRAM1	✓	☐	☐	☑	Used during boot by MCUboot for his memory stack.
Core/RAM	SRAM	SRAM2		☐	☐	☑	Used during boot by MCUboot to host DDR buffers used for DDR firmware installation
Core/RAM	LPSRAM	LPSRAM1		☐	☐
		LPSRAM2		☐	☐
		LPSRAM3		☐	☐
Core/Timers	TIM	TIMx (x = 1 to 8, 10 to 17, 20)		⬚	☐	⬚
Core/Timers	LPTIM	LPTIMx (x = 1 to 5)		⬚	⬚	⬚
Core/Watchdog	IWDG	IWDG1	☐	☐	☐
		IWDG2	☐	⬚	☐
		IWDG3				☐
		IWDG4				☐
		IWDG5
Core/Watchdog	WWDG	WWDG1				⬚
Core/Watchdog	WWDG	WWDG2
High speed interface	USB3DR	USB3DR		⬚	☐	⬚	The USB3DR can be used by U-Boot with command line tools.
High speed interface	USBH	USBH		⬚	☐	⬚
High speed interface	COMBOPHY	COMBOPHY		⬚	☐	⬚
High speed interface	UCPD	UCPD1		⬚	⬚	⬚
High speed interface	USB2PHY	USB2PHY1		⬚	☐	⬚	USB2PHY1 can be used in U-boot by USBH with command line tools.
High speed interface	USB2PHY	USB2PHY2		⬚	☐	⬚	USB2PHY2 can be used in U-boot by USB3DR with command line tools.
High speed interface	PCIE	PCIE		⬚	☐		The PCIe and the USB3DR running at USB3 speed are mutually exclusive. Both require using the ComboPHY.
Low speed interface	USART	UART4		☐	☐	☐
		UART5	☐	☐	☐	☐
		UART7		☐	☐	☐
		UART8	☐	☐	☐	☐
		UART9	☐	☐	☐	☐
		USART1		☐	☐	☐
		USART2	☐	☐	☐	☐
		USART3		☐	☐	☐
		USART6	☐	☐	☐	☐
Low speed interface	LPUART	LPUART1		⬚	⬚	⬚
Low speed interface	I2C	I2C1		☐	☐	☐
		I2C2		☐	☐	☐
		I2C3		☐	☐	☐
		I2C4		☐	☐	☐
		I2C5		☐	☐	☐
		I2C6		☐	☐	☐
		I2C7		☐	☐	☐
		I2C8		☐	☐	☐
Low speed interface	I3C	I3C1		⬚	⬚	⬚
		I3C2		⬚	⬚	⬚
		I3C3		⬚	⬚	⬚
		I3C4		⬚	⬚	⬚
Mass storage	OCTOSPI	OCTOSPI1	☐	☐	☐	☐
Mass storage	OCTOSPI	OCTOSPI2		☐	☐	☐
Mass storage	OCTOSPIM	OCTOSPIM	☐	☐	☐	☐
Mass storage	FMC	FMC	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Mass storage	SDMMC	SDMMC1	☐	☐	☐	☐
		SDMMC2	☐	☐	☐	☐
		SDMMC3			☐
Power & Thermal	RCC	RCC	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature For internal peripherals protected by a RISUP, the protection for reset and clock gating control is inherited from RIFSC configuration				RCC peripheral is used by all boot components. More info here
Power & Thermal	PWR	PWR	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Power & Thermal	DTS	DTS		⬚	⬚	⬚
Security	BSEC	BSEC	✓			✓
Security	RNG	RNG	✓	☐	⬚	☑
Security	HASH	HASH	✓	☐	☐	⬚
Security	CRYP	CRYP1	☑	⬚	⬚	⬚	ROM code allocation is managed with the bit 8 in OTP 16
Security	CRYP	CRYP2			⬚	⬚
Security	SAES	SAES	☐	☐	⬚	⬚	ROM code allocation is managed with the bit 8 in OTP 16
Security	TAMP	TAMP	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Security	OTFDEC	OTFDEC1		⬚	⬚	⬚
Security	OTFDEC	OTFDEC2		⬚	⬚	⬚
Security	PKA	PKA	✓	☐	⬚	⬚
Security	RIFSC	RIFSC	✓	☑	☑	☑
Security	RISAB	RISAB1	✓	✓	⬚
		RISAB2	✓	✓	⬚
		RISAB3	✓	⬚	⬚		Used by ROM code only in serial boot for USB buffer management
		RISAB4		⬚	⬚	☑	Used by MCUBoot for the DDR firmware buffer
		RISAB5	✓	⬚	⬚		Used by ROM code only during cold boot
		RISAB6		⬚	⬚
Security	RISAF	RISAF1		☐	⬚
		RISAF2		☐	⬚
		RISAF4		☐	⬚	☑	FSBL MCUboot configures Cortex-M secure and encrypted memory regions
		RISAF5		☐	⬚
Trace & debug	SERC	SERC		⬚	⬚	⬚
Visual	DSI	DSI	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Visual	LTDC	LTDC_CMN			☐
		LTDC_L1L2			☐
		LTDC_L3			⬚
		LTDC_ROT			⬚
Visual	LVDS	LVDS			☐
Core/RAM	VDERAM	VDERAM		☐	☐

3. Internal peripherals runtime assignment[edit | edit source]

Click on to expand or collapse the legend...

STM32MP25 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by the OpenSTLinux BSP:

⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
☐ means that the peripheral can be assigned to the given runtime context.
☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.

ADF internal peripheral

Domain	Peripheral	Runtime allocation						Comment
Domain	Peripheral	Instance	Cortex-A35 secure (OP-TEE / TF-A BL31)	Cortex-A35 nonsecure (Linux)	Cortex-M33 secure (TF-M)	Cortex-M33 nonsecure (STM32Cube)	Cortex-M0+ (STM32Cube)	Comment
Core/Processors	Arm^® Cortex^®-A35	Arm^® Cortex^®-A35	✓^OP-TEE ✓^{TF-A BL31}	✓	☐	⬚		In M33-TD flavor , Cortex-A35 can be started by TF-M or by STM32CubeMP2. Running the OpenSTLinux distribution.
Core/Processors	Arm^® Cortex^®-M33 (coprocessor)	Arm^® Cortex^®-M33 (coprocessor)			✓	☐
Core/Processors	Arm^® Cortex^®-M0+ (coprocessor)	Arm^® Cortex^®-M0+ (coprocessor)	⬚^OP-TEE	☐	⬚	⬚
Analog	VREFBUF	VREFBUF	⬚	⬚	☑	⬚		T-FM offers SCMI regulator service to manage VREFBUF
Analog	ADC	ADC12	☐^OP-TEE	☐	⬚	☐
Analog	ADC	ADC3	☐^OP-TEE	☐	⬚	☐
Analog	MDF	MDF1	⬚^OP-TEE	☐	⬚	☐
Audio	SAI	SAI1	⬚^OP-TEE	☐	⬚	☐
		SAI2	⬚^OP-TEE	☐	⬚	☐
		SAI3	⬚^OP-TEE	☐	⬚	☐
		SAI4	⬚^OP-TEE	☐	⬚	☐
Coprocessor	IPCC	IPCC1	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Coprocessor	IPCC	IPCC2	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core	STGEN	STGEN	☑^OP-TEE ☑^{TF-A BL31}	Read-only ^(STGENR)
Core	RTC	RTC	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature					RTC is mandatory to resynchronize STGEN after exiting low-power modes.
Core/DMA	HPDMA	HPDMAx (x = 1 to 3)	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core/DMA	LPDMA	LPDMA	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core/Interrupts	EXTI	EXTI1	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core/Interrupts	EXTI	EXTI2	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core/IOs	GPIO	GPIOA-K	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core/IOs	GPIO	GPIOZ	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core/RAM	SYSRAM	SYSRAM	☑^BL31 ☐^OP-TEE	☑	☐	☐		Cortex-A35 secure section required for low power entry and exit
Core/RAM	DDRCTRL & DDRPHYC	DDR			✓	⬚		Assignment is controlled by the RCC RIF 104 resource that also include the PLL2 control.
Core/RAM	SRAM	SRAM1	☑^OP-TEE ☐^BL31	☑	☑	☐		Bsec mirror, SCMI CID1 exchange area, PSA buffer. See STM32MP21_memory_mapping
Core/RAM	SRAM	SRAM2	☐^OP-TEE ☐^BL31	☐	☐	☐
Core/RAM	LPSRAM	LPSRAM1	☐^OP-TEE ☐^BL31	☐	☐	☐	☑	Should contain Cortex-M0+ firmware code
		LPSRAM2	☐^OP-TEE ☐^BL31	☐	☐	☐	☑	Should contain Cortex-M0+ firmware data
		LPSRAM3	☐^OP-TEE ☐^BL31	☐	☐	☐	☑
Core/Timers	TIM	TIMx (x = 1 to 8, 10 to 17, 20)	⬚^OP-TEE	☐	⬚	☐
Core/Timers	LPTIM	LPTIM1	☐^OP-TEE	☐	⬚	☐		LPTIM1 can be used for HSE monitoring.
		LPTIM2	☐^OP-TEE	☐	⬚	☐
		LPTIM3	☐^OP-TEE	☐	⬚	☐	☐	LPTIMy (y = 3, 4, 5) can be used for scheduling in low power modes by Linux
		LPTIM4	☐^OP-TEE	☐	⬚	☐	☐	LPTIMy (y = 3, 4, 5) can be used for scheduling in low power modes by Linux
		LPTIM5	☐^OP-TEE	☐	⬚	☐	☐	LPTIMy (y = 3, 4, 5) can be used for scheduling in low power modes by Linux
Core/Watchdog	IWDG	IWDG1	☐^OP-TEE ☐^{TF-A BL31}	☐
		IWDG2	☐^OP-TEE ☐^{TF-A BL31}	☐
		IWDG3			☐	☐
		IWDG4			☐	☐
		IWDG5					☐
Core/Watchdog	WWDG	WWDG1			⬚	☐
Core/Watchdog	WWDG	WWDG2					☐
High speed interface	USB3DR	USB3DR	⬚^OP-TEE	☐	⬚	⬚		The USB3DR running at USB3 speed and the PCIe are mutually exclusive. Both require to use the ComboPHY.
High speed interface	USBH	USBH	⬚^OP-TEE	☐	⬚	⬚
High speed interface	UCPD	UCPD1	⬚^OP-TEE	⬚	⬚	☐
High speed interface	COMBOPHY	COMBOPHY	⬚^OP-TEE	☐	⬚	⬚		COMBOPHY can be assigned to either the USB3DR or the PCIe.
High speed interface	USB2PHY	USB2PHY1	⬚^OP-TEE ⬚^{TF-A BL31}	☐	⬚	☐		Allocation inherited from USBH
High speed interface	USB2PHY	USB2PHY2	⬚^OP-TEE ☐^{TF-A BL31}	☐	⬚	☐		Allocation inherited from USB3DR
High speed interface	PCIE	PCIE	⬚^OP-TEE	☐				The PCIe and the USB3DR running at USB3 speed are mutually exclusive. Both require using the ComboPHY.
Low speed interface	USART	UART4	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		UART5	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		UART7	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		UART8	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		UART9	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		USART1	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		USART2	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		USART3	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		USART6	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
Low speed interface	LPUART	LPUART1	⬚^OP-TEE ⬚^{TF-A BL31}	☐	⬚	☐	☐
Low speed interface	I2C	I2C1	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐
		I2C2	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐
		I2C3	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐
		I2C4	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐
		I2C5	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐
		I2C6	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐
		I2C7	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐		Used for PMIC control on ST boards.
		I2C8	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐	☐
Low speed interface	I3C	I3C1	⬚^OP-TEE ⬚^{TF-A BL31}	☐	⬚	☐
		I3C2	⬚^OP-TEE ⬚^{TF-A BL31}	☐	⬚	☐
		I3C3	⬚^OP-TEE ⬚^{TF-A BL31}	☐	⬚	☐
		I3C4	⬚^OP-TEE ⬚^{TF-A BL31}	☐	⬚	☐	☐
Mass storage	OCTOSPI	OCTOSPI1	⬚^OP-TEE	☐	☐	☐		OP-TEE need to access OCTOSPI1 at boot time to set OSPIM mode
Mass storage	OCTOSPI	OCTOSPI2	⬚^OP-TEE	☐	☐	☐		OP-TEE need to access OCTOSPI2 at boot time to set OSPIM mode
Mass storage	OCTOSPIM	OCTOSPIM	☐^OP-TEE	☐	☐	☐
Mass storage	FMC	FMC	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Mass storage	SDMMC	SDMMC1	⬚^OP-TEE	☐	☐	☐
		SDMMC2	⬚^OP-TEE	☐	☐	☐
		SDMMC3	⬚^OP-TEE	☐	☐	☐
Power & Thermal	RCC	RCC	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature. For internal peripherals protected by a RISUP, the protection for reset and clock gating control is inherited from RIFSC configuration.					RCC peripheral is used by all software components. More info here. The Cortex-M secure OS TF-M controls the system resources and provides SCMI services.
Power & Thermal	PWR	PWR	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Power & Thermal	DTS	DTS	⬚^{TF-A BL31} ⬚^OP-TEE	☐	⬚	⬚
Security	BSEC	BSEC			✓
Security	RNG	RNG	☐^OP-TEE	⬚	☐	⬚
Security	HASH	HASH	☐^OP-TEE	☐	⬚	☐
Security	CRYP	CRYP1	☐^OP-TEE	☐	⬚	☐
Security	CRYP	CRYP2	☐^OP-TEE	☐	⬚	☐
Security	CRC	CRC	⬚^OP-TEE	☐	⬚	☐
Security	SAES	SAES	☐^OP-TEE	⬚	⬚	⬚
Security	TAMP	TAMP	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Security	OTFDEC	OTFDEC1	⬚^OP-TEE	⬚	⬚	⬚
Security	OTFDEC	OTFDEC2	⬚^OP-TEE	⬚	⬚	⬚
Security	PKA	PKA	☑^OP-TEE	⬚	⬚	⬚
Security	RIFSC	RIFSC	☑^OP-TEE	☑	☑	☐
Security	RISAB	RISAB1	☑^OP-TEE	⬚
		RISAB2	☑^OP-TEE	⬚
		RISAB3	☐^OP-TEE	⬚	☑	⬚
		RISAB4	☐^OP-TEE	⬚	☑	⬚
		RISAB5	☐^OP-TEE	⬚	☑	⬚
		RISAB6	☐^OP-TEE	⬚	☑	⬚
Security	RISAF	RISAF1	☐^OP-TEE	⬚	☑	⬚		TF-M configures all regions
		RISAF2	☐^OP-TEE	⬚	☑	⬚		TF-M configures all regions
		RISAF4	☐^OP-TEE	⬚	☑	⬚		TF-M configures all regions except its own
		RISAF5	☐^OP-TEE	⬚	☑	⬚		TF-M configures all regions
Trace & debug	SERC	SERC	☐^OP-TEE	⬚	☑	⬚
Trace & Debug	HDP	HDP	⬚^OP-TEE	☐	⬚	⬚
Visual	GPU	GPU	⬚^OP-TEE	☐	⬚	⬚
Visual	DSI	DSI	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Visual	LTDC	LTDC_CMN	⬚^OP-TEE	☐	⬚	☐
		LTDC_L1L2	⬚^OP-TEE	☐	⬚	☐
		LTDC_L3	☐^OP-TEE	☐	⬚	☐
		LTDC_ROT	⬚^OP-TEE	☐	⬚	☐
Visual	DCMI	DCMI	⬚^OP-TEE	☐	⬚	☐
Visual	CSI	CSI	⬚^OP-TEE	☐	⬚	☐
Visual	LVDS	LVDS	⬚^OP-TEE	☐	⬚	☐
Visual	DCMIPP	DCMIPP	⬚^OP-TEE	☐	⬚	☐
Visual	VENC	VENC	⬚^OP-TEE	☐	⬚	⬚
Visual	VDEC	VDEC	⬚^OP-TEE	☐	⬚	⬚
Core/RAM	VDERAM	VDERAM	☐^OP-TEE ☐^BL31	☐	☐	☐		Free for any use if video encoder and video decoder not used.

4. References[edit | edit source]

[1] STM32 MPU microprocessor devices: multiple-core architecture concepts

[2] STM32MP25 reference manuals

[1]

[2]