1. Purpose[edit | edit source]
This article explains how to change the GPU operating point (also known as OPP). An operating point corresponds to the frequency of the processor and the voltage that needs to be supplied to sustain it.
2. Hardware side[edit | edit source]
On STM32MP23x lines 
and STM32MP25x lines products, the GPU sub-system:
- is clocked by PLL3 from the RCC internal peripheral in OpenSTLinux
- is supplied with VDDGPU voltage provided by a PWR regulator
The part number tells the device maximum supported frequency with associated usage conditions:
- for STM32MP23
- up to 400 MHz, the nominal frequency
- for STM32MP25
- up to 800 MHz, the nominal frequency with nominal VDDGPU at 0.8V
- only for part numbers with overdrive support, the overdrive frequency is 900 MHz with VDDGPU at 0.9V
refer to the AN5729 document for impact of this overdrive GPU OPP on STM32MP25 life time usage.
3. Software side[edit | edit source]
In OpenSTLinux distribution, OP-TEE sets the GPU configuration used when the GPU sub-system, with associated SCMI power domain, is activated; that is the maximum frequency sustainable with the supported voltage and with a supported PLL3 configuration.
3.1. DT configuration (STM32/SoC level)[edit | edit source]
The GPU sub-system configuration is defined in the OP-TEE "soc" device tree file:
The GPU node references the used clock, supply and OPP table. The OPP table contains one or several frequency / voltage pair(s).
3.1.1. GPU node[edit | edit source]
&rifsc {
gpu: gpu@48280000 {
compatible = "vivante,gc";
gpu-supply = <&vddgpu>;
clocks = <&rcc CK_KER_GPU>;
operating-points-v2 = <&gpu_opp_table>;
access-controllers = <&rifsc STM32MP25_RIFSC_GPU_ID>;
};
};
3.1.2. OPP table[edit | edit source]
- OPP table for STM32MP23x lines :
/ {
gpu_opp_table: opp-table-gpu {
compatible = "operating-points-v2";
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <800000>;
opp-supported-hw = <0x3>;
st,opp-default;
};
};
};
- OPP table for STM32MP25x lines :
/ {
gpu_opp_table: opp-table-gpu {
compatible = "operating-points-v2";
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <800000>;
opp-supported-hw = <0x3>;
st,opp-default;
};
opp-900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <900000>;
opp-supported-hw = <0x2>;
};
};
};
The operating points are defined with the associated bit-field opp-supported-hw
- bit 0: supported by part number = STM32MP2xxA / STM32MP2xxC
- bit 1: supported by part number = STM32MP2xxD / STM32MP2xxF (overdrive support)
Notes:
- OP-TEE selects the highest st,opp-default supported OPP during the GPU activation.
3.2. DT configuration (board level)[edit | edit source]
The objective of this chapter is to explain how to change GPU system configuration, including supply and clock, for a given board.
This configuration should be done in specific board device tree files (board dts file).
3.2.1. VDDGPU voltage configuration[edit | edit source]
The external voltage VDDGPU is provided to the PWR internal peripheral, indicated in pwr node by the vddgpu-supply property in the vddgpu sub-node.
You can reduce the list of supported VDDGPU voltage for your board, for example when fixed or gpio regulator is used, the OPP GPU driver in OP-TEE will automatically skip the OPP for unsupported voltage.
 Information
|
| On STMicroelectronic boards, this voltage is provided by a STPMIC regulator with a range of supported voltage. Read PMIC article for device tree configuration. |
The example below sets STPMIC25 BUCK3 minimal voltage to 0.8 V and max to 0.9V, allowing to provided the expected nominal and overdrive voltage on PWR VDDGPU for the GPU on STM32MP25 board:
&pwr {
...
vddgpu: vddgpu {
status = "okay";
vddgpu-supply = <&vddgpu_pmic>;
};
};
...
pmic2: stpmic2@33 {
vddgpu_pmic: buck3 {
regulator-name = "vddgpu_pmic";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-over-current-protection;
};
};
3.2.2. PLL3 configuration[edit | edit source]
The PLL3 configurations needed to reach the above frequencies must be described via the st,ck_gpu, st,pll-3 and property in rcc device tree node on OP-TEE device tree.
See Clock device tree configuration for binding details.
For example in core/arch/arm/dts/stm32mp257f-dk-ca35tdcid-rcc.dtsi , generated by STM32MP2 clock tree:
pll3: st,pll-3 {
pll3_cfg_800Mhz: pll3-cfg-800Mhz {
cfg = <20 1 1 1>;
src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>;
};
pll3_cfg_900Mhz: pll3-cfg-900Mhz {
cfg = <45 2 1 1>;
src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>;
};
};
And in core/arch/arm/dts/stm32mp257f-dk.dts :
&rcc {
st,clk_opp {
...
st,ck_gpu {
cfg_1 {
hz = <800000000>;
st,pll = <&pll3_cfg_800Mhz>;
};
cfg_2 {
hz = <900000000>;
st,pll = <&pll3_cfg_900Mhz>;
};
};
};
};
You can reduce the list of supported PLL3 configuration for your board, the OPP GPU driver in OP-TEE will automatically skip the OPP for unsupported PLL3 frequency.
3.3. GPU OPP selection[edit | edit source]
By default OP-TEE selects the nominal GPU OPP at boot.
To select the overdrive GPU OPP on STM32MP25 for STM32MP25, in your OP-TEE board device tree, you indicate that the overdrive OPP opp-900000000 is sustainable with st,opp-default:
&opp-table-gpu {
opp-900000000 {
st,opp-default;
};
};
Refer to the AN5729 document for impact on life time usage of this overdrive GPU OPP with VDDGPU at 0.9V.
For ecosystem release v6.0.0 
[edit | edit source]
On ecosystem release v6.0.0 , the GPU OPP driver doesn't yet correctly manage the GPU clock and supply associated to GPU OPP, you must force the selected PLL3 configuration with st,pll property and force the VDDGPU supply value to respect the targeted GPU OPP.
For example to use overdrive frequency at 900MHz for GPU activation, you must change the initial configuration:
pll3: st,pll-3 {
st,pll = <&pll3_cfg_800Mhz>;
pll3_cfg_800Mhz: pll3-cfg-800Mhz {
cfg = <20 1 1 1>;
src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>;
};
pll3_cfg_900Mhz: pll3-cfg-900Mhz {
cfg = <45 2 1 1>;
src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>;
};
};
to
pll3: st,pll-3 {
st,pll = <&pll3_cfg_900Mhz>;
...
};
And also force the minimal VDDGPU voltage with:
&vddgpu_pmic {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
};
4. How to go further[edit | edit source]
- Clock device tree configuration (looks for "how to build a clock tree" according to your product)