Registered User m (Assignment tables reviewed with architects) |
Registered User mNo edit summary Tag: 2017 source edit |
||
(29 intermediate revisions by 5 users not shown) | |||
Line 1: | Line 1: | ||
<noinclude>{{ApplicableFor | <noinclude>{{ApplicableFor | ||
|MPUs list=STM32MP13x, STM32MP15x | |MPUs list=STM32MP13x, STM32MP15x, STM32MP21x, STM32MP23x, STM32MP25x | ||
|MPUs checklist=STM32MP13x,STM32MP15x | |MPUs checklist=STM32MP13x, STM32MP15x, STM32MP21x, STM32MP23x, STM32MP25x | ||
}}</noinclude> | }} | ||
</noinclude> | |||
==Article purpose== | ==Article purpose== | ||
Line 14: | Line 15: | ||
The '''GPIO''' peripheral is used to configure the device IO ports, also called pins or pads. <br /><br /> | The '''GPIO''' peripheral is used to configure the device IO ports, also called pins or pads. <br /><br /> | ||
On {{MicroprocessorDevice | device=13}}, each GPIO instance controls 16 pins (for GPIOA to GPIOG), 15 pins (for GPIOH) or 8 pins (for GPIOI).<br /> | On {{MicroprocessorDevice | device=13}}, each GPIO instance controls 16 pins (for GPIOA to GPIOG), 15 pins (for GPIOH) or 8 pins (for GPIOI).<br /> | ||
On {{MicroprocessorDevice | device=15}}, each GPIO instance controls 16 pins (for GPIOA to GPIOJ) or 8 pins (for GPIOK and GPIOZ).<br /><br /> | On {{MicroprocessorDevice | device=15}}, each GPIO instance controls 16 pins (for GPIOA to GPIOJ) or 8 pins (for GPIOK and GPIOZ).<br /> | ||
Every IO port implements the logic shown in the image below, taken from [[STM32MP15 resources#Reference manuals|STM32MP15 | On {{MicroprocessorDevice | device=25}}, each GPIO instance controls 16 pins (for GPIOA/B/D/E/F/G/I/J), 14 pins (for GPIOC), 12 pins (for GPIOH), 10 pins (for GPIOZ) or 8 pins (for GPIOK).<br /><br /> | ||
* The '''IO pin''' (on the right) is the physical connection to a chip external ball, soldered on the PCB. The link between each GPIO pin and each ball of the package is given in the datasheet | Every IO port implements the logic shown in the image below, taken from reference manual <ref name="STM32MP RM">Reference manuals: [[STM32MP15 resources#Reference manuals|STM32MP15]] | [[STM32MP13 resources#Reference manuals|STM32MP13]] | [[STM32MP25 resources#Reference manuals|STM32MP25]]</ref>. | ||
* The '''Read''' and '''Write''' accesses allow the processor (Arm<sup>®</sup> Cortex<sup>®</sup>-A7 | * The '''IO pin''' (on the right) is the physical connection to a chip external ball, soldered on the PCB. The link between each GPIO pin and each ball of the package is given in the datasheet <ref name="STM32MP datasheet">Datasheets: [[STM32MP13 resources#Datasheets|STM32MP13]] | [[STM32MP15 resources#Datasheets|STM32MP15]] | [[STM32MP25 resources#Datasheets|STM32MP25]]</ref>. | ||
* The '''Read''' and '''Write''' accesses allow the processor (Arm<sup>®</sup> Cortex<sup>®</sup>-A7 for {{MicroprocessorDevice | device=1}} or Arm<sup>®</sup> Cortex<sup>®</sup>-M4 for {{MicroprocessorDevice | device=15}}) to configure the peripheral, control the IO pin and get its status. | |||
* '''Alternate function''' (AF) links allow to connect the IO port to an internal peripheral digital line. In such a case, the IO direction is given by the line purpose: for instance, [[USART internal peripheral|UART]] transmit line (TX) is an output. | * '''Alternate function''' (AF) links allow to connect the IO port to an internal peripheral digital line. In such a case, the IO direction is given by the line purpose: for instance, [[USART internal peripheral|UART]] transmit line (TX) is an output. | ||
* '''Analog''' links allow to connect the IO port to an internal peripheral analog line. In such a case, the IO direction is given by the line purpose: for instance, [[ADC internal peripheral|ADC]] input line is an input.<br /><br /> | * '''Analog''' links allow to connect the IO port to an internal peripheral analog line. In such a case, the IO direction is given by the line purpose: for instance, [[ADC internal peripheral|ADC]] input line is an input.<br /><br /> | ||
Line 32: | Line 35: | ||
** '''alternate function''' (AF). | ** '''alternate function''' (AF). | ||
* selecting the '''alternate function''' in the GPIOx_AFRH/L register (only when the pin mode is AF): | * selecting the '''alternate function''' in the GPIOx_AFRH/L register (only when the pin mode is AF): | ||
** each IO port can support up to 16 alternate functions that are documented in the datasheet | ** each IO port can support up to 16 alternate functions that are documented in the datasheet <ref name="STM32MP datasheet" />. | ||
* setting the '''pin characteristics''': | * setting the '''pin characteristics''': | ||
** '''no pull-up and no pull-down''' or '''pull-up''' or '''pull-down''' in the GPIOx_PUPDR register, needs to be selected to be coherent with the hardware schematics. | ** '''no pull-up and no pull-down''' or '''pull-up''' or '''pull-down''' in the GPIOx_PUPDR register, needs to be selected to be coherent with the hardware schematics. | ||
** '''push-pull''' or '''open-drain''' in the GPIOx_OTYPER register, needs to be selected to be coherent with the hardware schematics. | ** '''push-pull''' or '''open-drain''' in the GPIOx_OTYPER register, needs to be selected to be coherent with the hardware schematics. | ||
** '''output speed''' in the GPIOx_OSPEEDR register needs to be tuned to achieve the expected level of performance (rising and falling times) while limiting electromagnetic interferences (EMI) and overconsumption. As example, the table below summarizes the maximum achievable frequency for each supported IO voltage and a 30pF load: | ** '''output speed''' in the GPIOx_OSPEEDR register needs to be tuned to achieve the expected level of performance (rising and falling times) while limiting electromagnetic interferences (EMI) and overconsumption. As example, the table below summarizes the maximum achievable frequency for each supported IO voltage and a '''30pF load''': | ||
::* On {{MicroprocessorDevice | device=13}}: | ::* On {{MicroprocessorDevice | device=13}}: | ||
:::{| class="st-table" width="60%" | :::{| class="st-table" width="60%" | ||
Line 62: | Line 65: | ||
|- | |- | ||
| align="center" | b11 || Very high speed || 150 MHz || 70 MHz || 111 MHz | | align="center" | b11 || Very high speed || 150 MHz || 70 MHz || 111 MHz | ||
|} | |||
::* On {{MicroprocessorDevice | device=25}}: | |||
:::{| class="st-table" width="60%" | |||
|- | |||
! width="20%" | GPIOx_OSPEEDR !! width="20%" | Meaning !! width="20%" | VDD=3v3 !! width="20%" | VDD=1v8<br />VRSEL OFF !! width="20%" | VDD=1v8<br />VRSEL ON | |||
|- | |||
| align="center" | b00 || Low speed || 45 MHz || 20 MHz || 45 MHz | |||
|- | |||
| align="center" | b01 || Medium speed || 70 MHz || 25 MHz || 70 MHz | |||
|- | |||
| align="center" | b10 || High speed || 100 MHz || 30 MHz || 100 MHz | |||
|- | |||
| align="center" | b11 || Very high speed || 120 MHz || 45 MHz || 120 MHz | |||
|} | |} | ||
:Notes: | :Notes: | ||
:* More information is available in the '''IO speed settings''' chapter of the "''Getting started with...''" Application Note ([[STM32MP13 resources# | :* More information is available in the '''IO speed settings''' chapter of the "''Getting started with...''" <ref name="STM32MP hardware development"> | ||
:* There are different '''IO types''' with different characteristics: for instance, all pads are not able to achieve 150 MHz while supplied at | Application Note (''Getting started with ... hardware development''): <br /> | ||
:* | * [[STM32MP13 resources#AN5474|AN5474]] for {{MicroprocessorDevice | device=13}}<br /> | ||
* [[STM32MP15 resources#AN5031|AN5031]] for {{MicroprocessorDevice | device=15}}<br /> | |||
* [[STM32MP25 resources#AN5489|AN5489]] for {{MicroprocessorDevice | device=25}} | |||
</ref>. | |||
:* There are different '''IO types''' with different characteristics: for instance, all pads are not able to achieve 150 MHz while supplied at 3.3V. Refer to the datasheet <ref name="STM32MP datasheet" /> to get the characteristics for each pin. | |||
:* On {{MicroprocessorDevice | device=1}}, when supplied with VDD=1.8V, it is possible to enable the '''high speed low voltage''' (HSLV) pad mode for FTH (Five volt Tolerant High speed) and FTE (Five volt Tolerant Extended high speed) IO types on some peripherals via [[SYSCFG internal peripheral|SYSCFG]] HSLVEN bits. '''Warning''': As it could be destructive if used when VDD>2.7V, thanks to carefully read the HSLVEN bits documentation in reference manuals <ref name="STM32MP RM" />, especially the management of the OTP bit PRODUCT_BELOW_2V5 ({{MicroprocessorDevice | device=1}}) and lock mechanism (for {{MicroprocessorDevice | device=13}} only). | |||
:* On {{MicroprocessorDevice | device=2}}, IOs could be configured either 1.8V or 3.3V compliance modes. | |||
:** In 1.8V mode, IOs are not 3.3V tolerant | |||
:** In 3.3V mode, IOs are not 5V tolerant | |||
:** By default, all IOs are in 3.3V mode, working in non-optimal condition when supplied with VDD=1.8V. It is responsibility of [[Boot chain overview|boot chain]] to configure IOs mode according to product configuration by setting PWR VRSEL bits for each IO domain. | |||
:** '''Warning''': PWR VRSEL bits have effect only if associated HSLV OTP bit have been programmed. | |||
:** '''Warning''': Enabling 1.8V mode when VDD=3.3V will damage IOs | |||
The table below shows all possible characteristics combinations for each '''pin mode''': | The table below shows all possible characteristics combinations for each '''pin mode''': | ||
Line 95: | Line 122: | ||
:* On the other hand, leaving a register not initialized whereas it should be, may lead to an unpredictable behavior! | :* On the other hand, leaving a register not initialized whereas it should be, may lead to an unpredictable behavior! | ||
Refer to the | GPIO access configuration | ||
*On {{MicroprocessorDevice | device=13}}, any IOs from all GPIO banks can be unitary defined as secure or non-secure. | |||
*On {{MicroprocessorDevice | device=15}}, only IOs from GPIOZ can be unitary defined as secure or non-secure. | |||
*On {{MicroprocessorDevice | device=25}}, GPIO are RIF-aware, that means it is possible to assign each GPIO to one execution context define by: | |||
:* a security level | |||
:* a privilege level | |||
:* a CID | |||
:For more information about RIF please refer to [[Resource Isolation Framework overview]]. | |||
Refer to the '''STM32 MPU reference manuals''' <ref name="STM32MP RM" /> for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented. | |||
==Peripheral usage== | ==Peripheral usage== | ||
Line 101: | Line 137: | ||
===Boot time assignment=== | ===Boot time assignment=== | ||
The [[STM32CubeMX]] tool allows to configure in one place the GPIO configuration | The [[STM32CubeMX]] tool allows to configure in one place the GPIO configuration for boot time and runtime, so it is highly recommended to use it to generate your [[Device tree|device tree]]. Moreover, [[STM32CubeMX]] integrates all the information documented in the datasheet <ref name="STM32MP datasheet" />, making this configuration step straightforward. | ||
<br /><br /> | <br /><br /> | ||
Since a GPIO configuration is done via atomic registers read and write, concurrent accesses from different cores must be avoided | Since a GPIO configuration is done via atomic registers read and write, concurrent accesses from different cores must be avoided. | ||
* On {{MicroprocessorDevice | device=15}} all GPIO configurations are done by the Arm<sup>®</sup> Cortex<sup>®</sup>-A7. | |||
* On {{MicroprocessorDevice | device=25}}, GPIO configurations could be done by the different execution contexts as soon as RIF configuration has been applied by main processor (TDCID) secure OS. | |||
The strategy is to progressively initialize the GPIO all along the [[Boot chain overview|boot chain]], as soon as one boot component needs to use them: | |||
* Most of the GPIOs used by the [[STM32 MPU ROM code overview|ROM code]] are directly defined in the ROM code but it is possible to change some pins muxing via dedicated words in [[BSEC internal peripheral|BSEC]]. | * Most of the GPIOs used by the [[STM32 MPU ROM code overview|ROM code]] are directly defined in the ROM code but it is possible to change some pins muxing via dedicated words in [[BSEC internal peripheral|BSEC]]. | ||
* The other boot components are relying on a common binding<ref>{{CodeSource | Linux kernel | Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml| Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml}}</ref> in the [[Device tree|device tree]] to get the pins configuration: | * The other boot components are relying on a common binding<ref>{{CodeSource | Linux kernel | Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml| Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml}}</ref> in the [[Device tree|device tree]] to get the pins configuration: | ||
** The [[Boot chain overview|FSBL]] configures both secure and non-secure pins according to peripherals firewall configuration. | |||
** The [[Boot chain overview|Secure OS]] configures pins firewall protection and secure pins for secure peripherals | |||
** The [[Boot chain overview|SSBL]] and Linux [[Pinctrl overview|pinctrl]] only configure non-secure pins. | ** The [[Boot chain overview|SSBL]] and Linux [[Pinctrl overview|pinctrl]] only configure non-secure pins. | ||
*** On {{MicroprocessorDevice | device=15}}, Linux also initializes the GPIO used by the coprocessor, via its [[Resource_manager_for_coprocessing#Resource_management_on_the_Cortex-M_firmware|resource manager]]. | *** On {{MicroprocessorDevice | device=15}}, Linux also initializes the GPIO used by the coprocessor, via its [[Resource_manager_for_coprocessing#Resource_management_on_the_Cortex-M_firmware|resource manager]]. | ||
Line 143: | Line 183: | ||
|- | |- | ||
<section end=stm32mp15_boottime /> | <section end=stm32mp15_boottime /> | ||
|} | |||
====On {{MicroprocessorDevice | device=21}}==== | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp2_a35_boottime}} | |||
<section begin=stm32mp21_a35_boottime /> | |||
| rowspan="1" | Core/IOs | |||
| rowspan="1" | [[GPIO internal peripheral | GPIO]] <span title="RIF-aware internal peripheral"><sup>[[File:Info.png|15px|link=]]</sup> | |||
| GPIO | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| Shareable at internal peripheral level thanks to the RIF: see the [[GPIO internal peripheral#stm32mp21_GPIO_a35_boottime_rif | boot time allocation per feature]] | |||
|- | |||
<section end=stm32mp21_a35_boottime /> | |||
|} | |||
<span id="stm32mp21_GPIO_a35_boottime_rif"/>The below table shows the possible boot time allocations for the features of the GPIO instance. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp2_a35_boottime_rif}} | |||
| GPIOA-I IOy | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOZ IOy | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
|} | |||
====On {{MicroprocessorDevice | device=23}}==== | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp2_a35_boottime}} | |||
<section begin=stm32mp23_a35_boottime /> | |||
| rowspan="1" | Core/IOs | |||
| rowspan="1" | [[GPIO internal peripheral | GPIO]] <span title="RIF-aware internal peripheral"><sup>[[File:Info.png|15px|link=]]</sup> | |||
| GPIO | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| Shareable at internal peripheral level thanks to the RIF: see the [[GPIO internal peripheral#stm32mp23_GPIO_a35_boottime_rif | boot time allocation per feature]] | |||
|- | |||
<section end=stm32mp23_a35_boottime /> | |||
|} | |||
<span id="stm32mp23_GPIO_a35_boottime_rif"/>The below table shows the possible boot time allocations for the features of the GPIO instance. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp2_a35_boottime_rif}} | |||
| GPIOA-K IOy | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOZ IOy | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
|} | |||
====On {{MicroprocessorDevice | device=25}}==== | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp2_a35_boottime}} | |||
<section begin=stm32mp25_a35_boottime /> | |||
| rowspan="1" | Core/IOs | |||
| rowspan="1" | [[GPIO internal peripheral | GPIO]] <span title="RIF-aware internal peripheral"><sup>[[File:Info.png|15px|link=]]</sup> | |||
| GPIO | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| Shareable at internal peripheral level thanks to the RIF: see the [[GPIO internal peripheral#stm32mp25_GPIO_a35_boottime_rif | boot time allocation per feature]] | |||
|- | |||
<section end=stm32mp25_a35_boottime /> | |||
|} | |||
<span id="stm32mp25_GPIO_a35_boottime_rif"/>The below table shows the possible boot time allocations for the features of the GPIO instance. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp2_a35_boottime_rif}} | |||
| GPIOA-K IOy | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOZ IOy | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
|} | |} | ||
Line 148: | Line 280: | ||
The '''GPIO configuration''' must not be done from different cores to avoid concurrent accesses, but this is not the case for the '''GPIO using''': each core can manipulate IO on its own since dedicated set/clear registers are available for that.<br /> | The '''GPIO configuration''' must not be done from different cores to avoid concurrent accesses, but this is not the case for the '''GPIO using''': each core can manipulate IO on its own since dedicated set/clear registers are available for that.<br /> | ||
<br /> | <br /> | ||
Nevertheless, beyond the boot time, the GPIO configuration also evolves at runtime: while entering in [[Power overview|low power mode]], some GPIOs may be put back to analog input mode in order to reduce the power consumption. | Nevertheless, beyond the boot time, the GPIO configuration also evolves at runtime: while entering in [[Power overview|low power mode]], some GPIOs may be put back to analog input mode in order to reduce the power consumption. | ||
# the Arm<sup>®</sup> Cortex<sup>®</sup>- | </br>On {{MicroprocessorDevice | device=1}}, this is done in two times: | ||
# the Arm<sup>®</sup> Cortex<sup>®</sup>- | # the Arm<sup>®</sup> Cortex<sup>®</sup>-A non-secure takes care of the non-secure pins with Linux [[Overview of GPIO pins|IOs pins]] frameworks. | ||
# the Arm<sup>®</sup> Cortex<sup>®</sup>-A secure takes care of the secure pins. | |||
On wakeup, the [[Boot chain overview|boot chain]] restores the GPIO configuration similarly to what is done at boot time. | On wakeup, the [[Boot chain overview|boot chain]] restores the GPIO configuration similarly to what is done at boot time. | ||
</br>On {{MicroprocessorDevice | device=25}}, thanks to the RIF, each SW component shall take care of its pins during low power entry and exit sequences. | |||
=====On {{MicroprocessorDevice | device=13}}===== | =====On {{MicroprocessorDevice | device=13}}===== | ||
Line 184: | Line 320: | ||
|- | |- | ||
<section end=stm32mp15_runtime /> | <section end=stm32mp15_runtime /> | ||
|} | |||
====On {{MicroprocessorDevice | device=21}}==== | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp21_runtime}} | |||
<section begin=stm32mp21_a35_runtime /> | |||
| rowspan="1" | Core/IOs | |||
| rowspan="1" | [[GPIO internal peripheral | GPIO]] <span title="RIF-aware internal peripheral"><sup>[[File:Info.png|15px|link=]]</sup> | |||
| GPIO | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| Shareable at internal peripheral level thanks to the RIF: see the [[GPIO internal peripheral#stm32mp21_GPIO_a35_runtime_rif | runtime allocation per feature]] | |||
|- | |||
<section end=stm32mp21_a35_runtime /> | |||
|} | |||
<span id="stm32mp21_GPIO_a35_runtime_rif"/>The below table shows the possible runtime allocations for the features of the GPIO instance. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp21_runtime_rif}} | |||
| GPIOA-I IOy | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup><br/> <span title="assignable peripheral" style="font-size:21px">☐</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOZ IOy | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup><br/> <span title="assignable peripheral" style="font-size:21px">☐</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
|} | |||
====On {{MicroprocessorDevice | device=23}}==== | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp23_runtime}} | |||
<section begin=stm32mp23_a35_runtime /> | |||
| rowspan="1" | Core/IOs | |||
| rowspan="1" | [[GPIO internal peripheral | GPIO]] <span title="RIF-aware internal peripheral"><sup>[[File:Info.png|15px|link=]]</sup> | |||
| GPIO | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| Shareable at internal peripheral level thanks to the RIF: see the [[GPIO internal peripheral#stm32mp23_GPIO_a35_runtime_rif | runtime allocation per feature]] | |||
|- | |||
<section end=stm32mp23_a35_runtime /> | |||
|} | |||
<span id="stm32mp23_GPIO_a35_runtime_rif"/>The below table shows the possible runtime allocations for the features of the GPIO instance. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp23_runtime_rif}} | |||
| GPIOA-K IOy | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup><br/> <span title="assignable peripheral" style="font-size:21px">☐</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| GPIOZ IOy | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup><br/> <span title="assignable peripheral" style="font-size:21px">☐</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
|} | |||
====On {{MicroprocessorDevice | device=25}}==== | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp25_runtime}} | |||
<section begin=stm32mp25_a35_runtime /> | |||
| rowspan="1" | Core/IOs | |||
| rowspan="1" | [[GPIO internal peripheral | GPIO]] <span title="RIF-aware internal peripheral"><sup>[[File:Info.png|15px|link=]]</sup> | |||
| GPIO | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| Shareable at internal peripheral level thanks to the RIF: see the [[GPIO internal peripheral#stm32mp25_GPIO_a35_runtime_rif | runtime allocation per feature]] | |||
|- | |||
<section end=stm32mp25_a35_runtime /> | |||
|} | |||
<span id="stm32mp25_GPIO_a35_runtime_rif"/>The below table shows the possible runtime allocations for the features of the GPIO instance. | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp25_runtime_rif}} | |||
| GPIOA-K IOy | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup><br/> <span title="assignable peripheral" style="font-size:21px">☐</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| - | |||
| | |||
|- | |||
| GPIOZ IOy | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup><br/> <span title="assignable peripheral" style="font-size:21px">☐</span><sup>TF-A BL31</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
|} | |} | ||
Line 191: | Line 428: | ||
* '''Linux<sup>®</sup>''': [[Overview of GPIO pins|Linux IOs pins overview]] | * '''Linux<sup>®</sup>''': [[Overview of GPIO pins|Linux IOs pins overview]] | ||
* '''OP-TEE''': {{CodeSource | OP-TEE_OS | core/drivers/stm32_gpio.c | GPIO OP-TEE driver}} and {{CodeSource | OP-TEE_OS | core/include/drivers/stm32_gpio.h | header file of GPIO OP-TEE driver}} | * '''OP-TEE''': {{CodeSource | OP-TEE_OS | core/drivers/stm32_gpio.c | GPIO OP-TEE driver}} and {{CodeSource | OP-TEE_OS | core/include/drivers/stm32_gpio.h | header file of GPIO OP-TEE driver}} | ||
* '''STM32Cube''': [[ | * '''STM32Cube''': [[STM32CubeMP15 Package architecture|GPIO HAL driver]] and {{CodeSource | STM32CubeMP1 | Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_gpio.h | header file of GPIO HAL module}} | ||
* '''TF-A BL2''': {{CodeSource | TF-A | drivers/st/gpio/stm32_gpio.c | GPIO driver}} and {{CodeSource | TF-A | include/drivers/st/stm32_gpio.h | header file of GPIO driver}} | * '''TF-A BL2''': {{CodeSource | TF-A | drivers/st/gpio/stm32_gpio.c | GPIO driver}} and {{CodeSource | TF-A | include/drivers/st/stm32_gpio.h | header file of GPIO driver}} | ||
* '''U-Boot''': {{CodeSource | U-Boot | drivers/gpio/stm32_gpio.c | GPIO driver}} and {{CodeSource | U-Boot | drivers/gpio/stm32_gpio_priv.h | header file of GPIO driver}} | * '''U-Boot''': {{CodeSource | U-Boot | drivers/gpio/stm32_gpio.c | GPIO driver}} and {{CodeSource | U-Boot | drivers/gpio/stm32_gpio_priv.h | header file of GPIO driver}} | ||
* '''TF-M''': {{CodeSource | TF-M | platform/ext/target/stm/common/stm32mp2/native_driver/src/pinctrl/stm32_pinctrl.c | GPIO driver}} and {{CodeSource | TF-M | platform/ext/target/stm/common/stm32mp2/native_driver/include/stm32_gpio.h | header file of GPIO driver}} | |||
==How to assign and configure the peripheral== | ==How to assign and configure the peripheral== |
Latest revision as of 10:45, 7 November 2024
1. Article purpose[edit | edit source]
The purpose of this article is to:
- briefly introduce the GPIO peripheral and its main features,
- indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
- list the software frameworks and drivers managing the peripheral,
- explain how to configure the peripheral.
2. Peripheral overview[edit | edit source]
The GPIO peripheral is used to configure the device IO ports, also called pins or pads.
On STM32MP13x lines , each GPIO instance controls 16 pins (for GPIOA to GPIOG), 15 pins (for GPIOH) or 8 pins (for GPIOI).
On STM32MP15x lines , each GPIO instance controls 16 pins (for GPIOA to GPIOJ) or 8 pins (for GPIOK and GPIOZ).
On STM32MP25 unknown microprocessor device, each GPIO instance controls 16 pins (for GPIOA/B/D/E/F/G/I/J), 14 pins (for GPIOC), 12 pins (for GPIOH), 10 pins (for GPIOZ) or 8 pins (for GPIOK).
Every IO port implements the logic shown in the image below, taken from reference manual [1].
- The IO pin (on the right) is the physical connection to a chip external ball, soldered on the PCB. The link between each GPIO pin and each ball of the package is given in the datasheet [2].
- The Read and Write accesses allow the processor (Arm® Cortex®-A7 for STM32MP1 Series or Arm® Cortex®-M4 for STM32MP15x lines
) to configure the peripheral, control the IO pin and get its status.
- Alternate function (AF) links allow to connect the IO port to an internal peripheral digital line. In such a case, the IO direction is given by the line purpose: for instance, UART transmit line (TX) is an output.
- Analog links allow to connect the IO port to an internal peripheral analog line. In such a case, the IO direction is given by the line purpose: for instance, ADC input line is an input.
- Note:
- the pull-up and pull-down resistors are disabled (by hardware) in analog mode.
- at reset, all pins are set in analog input mode to protect the device and minimize the power consumption. All unused pins should be kept in this state.
The pin configuration done by the software consists in:
- setting the pin mode in the GPIOx_MODER register:
- input or output if the pin is used as general purpose (GPIO), controlled by software.
- analog.
- alternate function (AF).
- selecting the alternate function in the GPIOx_AFRH/L register (only when the pin mode is AF):
- each IO port can support up to 16 alternate functions that are documented in the datasheet [2].
- setting the pin characteristics:
- no pull-up and no pull-down or pull-up or pull-down in the GPIOx_PUPDR register, needs to be selected to be coherent with the hardware schematics.
- push-pull or open-drain in the GPIOx_OTYPER register, needs to be selected to be coherent with the hardware schematics.
- output speed in the GPIOx_OSPEEDR register needs to be tuned to achieve the expected level of performance (rising and falling times) while limiting electromagnetic interferences (EMI) and overconsumption. As example, the table below summarizes the maximum achievable frequency for each supported IO voltage and a 30pF load:
GPIOx_OSPEEDR Meaning VDD=3v3 VDD=1v8
HSLV OFFVDD=1v8
HSLV ONb00 Low speed 21 MHz 5 MHz 23 MHz b01 Medium speed 44 MHz 15 MHz 44 MHz b10 High speed 100 MHz 37 MHz 90 MHz b11 Very high speed 166 MHz 50 MHz 133 MHz
GPIOx_OSPEEDR Meaning VDD=3v3 VDD=1v8
HSLV OFFVDD=1v8
HSLV ONb00 Low speed 24 MHz 11 MHz 22 MHz b01 Medium speed 83 MHz 28 MHz 79 MHz b10 High speed 125 MHz 66 MHz 101 MHz b11 Very high speed 150 MHz 70 MHz 111 MHz
- On STM32MP25 unknown microprocessor device:
GPIOx_OSPEEDR Meaning VDD=3v3 VDD=1v8
VRSEL OFFVDD=1v8
VRSEL ONb00 Low speed 45 MHz 20 MHz 45 MHz b01 Medium speed 70 MHz 25 MHz 70 MHz b10 High speed 100 MHz 30 MHz 100 MHz b11 Very high speed 120 MHz 45 MHz 120 MHz
- Notes:
- More information is available in the IO speed settings chapter of the "Getting started with..." [3].
- There are different IO types with different characteristics: for instance, all pads are not able to achieve 150 MHz while supplied at 3.3V. Refer to the datasheet [2] to get the characteristics for each pin.
- On STM32MP1 Series, when supplied with VDD=1.8V, it is possible to enable the high speed low voltage (HSLV) pad mode for FTH (Five volt Tolerant High speed) and FTE (Five volt Tolerant Extended high speed) IO types on some peripherals via SYSCFG HSLVEN bits. Warning: As it could be destructive if used when VDD>2.7V, thanks to carefully read the HSLVEN bits documentation in reference manuals [1], especially the management of the OTP bit PRODUCT_BELOW_2V5 (STM32MP1 Series) and lock mechanism (for STM32MP13x lines
only).
- On STM32MP2 unknown microprocessor device, IOs could be configured either 1.8V or 3.3V compliance modes.
- In 1.8V mode, IOs are not 3.3V tolerant
- In 3.3V mode, IOs are not 5V tolerant
- By default, all IOs are in 3.3V mode, working in non-optimal condition when supplied with VDD=1.8V. It is responsibility of boot chain to configure IOs mode according to product configuration by setting PWR VRSEL bits for each IO domain.
- Warning: PWR VRSEL bits have effect only if associated HSLV OTP bit have been programmed.
- Warning: Enabling 1.8V mode when VDD=3.3V will damage IOs
The table below shows all possible characteristics combinations for each pin mode:
pin mode GPIOx_PUPDR GPIOx_OTYPER GPIOx_OSPEEDR analog
Not applicable Not applicable Not applicable input (GPIO or AF)
no pull-up and no pull-down
or pull-down
or pull-upNot applicable Not applicable output (GPIO or AF)
or bi-directional (AF)push-pull
or open-draincf. the table above
- Note:
- 'Not applicable' means that setting this register has no effect but, in any case, there is no risk for the device.
- On the other hand, leaving a register not initialized whereas it should be, may lead to an unpredictable behavior!
GPIO access configuration
- On STM32MP13x lines
, any IOs from all GPIO banks can be unitary defined as secure or non-secure.
- On STM32MP15x lines
, only IOs from GPIOZ can be unitary defined as secure or non-secure.
- On STM32MP25 unknown microprocessor device, GPIO are RIF-aware, that means it is possible to assign each GPIO to one execution context define by:
- a security level
- a privilege level
- a CID
- For more information about RIF please refer to Resource Isolation Framework overview.
Refer to the STM32 MPU reference manuals [1] for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.
3. Peripheral usage[edit | edit source]
This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm® Cortex®-A processor(s), and the STM32CubeMPU Package running on the Arm® Cortex®-M processor.
3.1. Boot time assignment[edit | edit source]
The STM32CubeMX tool allows to configure in one place the GPIO configuration for boot time and runtime, so it is highly recommended to use it to generate your device tree. Moreover, STM32CubeMX integrates all the information documented in the datasheet [2], making this configuration step straightforward.
Since a GPIO configuration is done via atomic registers read and write, concurrent accesses from different cores must be avoided.
- On STM32MP15x lines
all GPIO configurations are done by the Arm® Cortex®-A7.
- On STM32MP25 unknown microprocessor device, GPIO configurations could be done by the different execution contexts as soon as RIF configuration has been applied by main processor (TDCID) secure OS.
The strategy is to progressively initialize the GPIO all along the boot chain, as soon as one boot component needs to use them:
- Most of the GPIOs used by the ROM code are directly defined in the ROM code but it is possible to change some pins muxing via dedicated words in BSEC.
- The other boot components are relying on a common binding[4] in the device tree to get the pins configuration:
- The FSBL configures both secure and non-secure pins according to peripherals firewall configuration.
- The Secure OS configures pins firewall protection and secure pins for secure peripherals
- The SSBL and Linux pinctrl only configure non-secure pins.
- On STM32MP15x lines
, Linux also initializes the GPIO used by the coprocessor, via its resource manager.
- On STM32MP15x lines
3.1.1. On STM32MP13x lines
[edit | edit source]
Click on the right to expand the legend...
Domain | Peripheral | Boot time allocation | Comment | |||
---|---|---|---|---|---|---|
Instance | Cortex-A7 secure (ROM code) |
Cortex-A7 secure (TF-A BL2) |
Cortex-A7 non-secure (U-Boot) | |||
Core/IOs | GPIO | GPIOA-I | ✓ | ☑ | ☐ | The pins can individually be secured |
3.1.2. On STM32MP15x lines
[edit | edit source]
Click on the right to expand the legend...
Domain | Peripheral | Boot time allocation | Comment | |||
---|---|---|---|---|---|---|
Instance | Cortex-A7 secure (ROM code) |
Cortex-A7 secure (TF-A BL2) |
Cortex-A7 non-secure (U-Boot) | |||
Core/IOs | GPIO | GPIOA-K | ✓ | ☑ (*) | ☐ | The pins cannot be secured (*): despite they cannot be secured, the pins can be used by the secure context |
GPIOZ | ☐ | ☐ | The pins can individually be secured |
3.1.1. On STM32MP21 unknown microprocessor device[edit | edit source]
Click on to expand or collapse the legend...
Domain | Peripheral | Boot time allocation | Comment ![]() | |||
---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | |||
Core/IOs | GPIO ![]() |
GPIO | ☐ | ☐ | ☐ | Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature |
The below table shows the possible boot time allocations for the features of the GPIO instance.
Feature | Boot time allocation ![]() |
Comment | ||
---|---|---|---|---|
Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | ||
GPIOA-I IOy | ✓ | ☐ | ☐ | |
GPIOZ IOy | ☐ | ☐ |
3.1.2. On STM32MP23 unknown microprocessor device[edit | edit source]
Click on to expand or collapse the legend...
Domain | Peripheral | Boot time allocation | Comment ![]() | |||
---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | |||
Core/IOs | GPIO ![]() |
GPIO | ☐ | ☐ | ☐ | Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature |
The below table shows the possible boot time allocations for the features of the GPIO instance.
Feature | Boot time allocation ![]() |
Comment | ||
---|---|---|---|---|
Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | ||
GPIOA-K IOy | ✓ | ☐ | ☐ | |
GPIOZ IOy | ☐ | ☐ |
3.1.3. On STM32MP25 unknown microprocessor device[edit | edit source]
Click on to expand or collapse the legend...
Domain | Peripheral | Boot time allocation | Comment ![]() | |||
---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | |||
Core/IOs | GPIO ![]() |
GPIO | ☐ | ☐ | ☐ | Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature |
The below table shows the possible boot time allocations for the features of the GPIO instance.
Feature | Boot time allocation ![]() |
Comment | ||
---|---|---|---|---|
Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | ||
GPIOA-K IOy | ✓ | ☐ | ☐ | |
GPIOZ IOy | ☐ | ☐ |
3.2. Runtime assignment[edit | edit source]
The GPIO configuration must not be done from different cores to avoid concurrent accesses, but this is not the case for the GPIO using: each core can manipulate IO on its own since dedicated set/clear registers are available for that.
Nevertheless, beyond the boot time, the GPIO configuration also evolves at runtime: while entering in low power mode, some GPIOs may be put back to analog input mode in order to reduce the power consumption.
On STM32MP1 Series, this is done in two times:
- the Arm® Cortex®-A non-secure takes care of the non-secure pins with Linux IOs pins frameworks.
- the Arm® Cortex®-A secure takes care of the secure pins.
On wakeup, the boot chain restores the GPIO configuration similarly to what is done at boot time.
On STM32MP25 unknown microprocessor device, thanks to the RIF, each SW component shall take care of its pins during low power entry and exit sequences.
3.2.1. On STM32MP13x lines
[edit | edit source]
Click on the right to expand the legend...
Domain | Peripheral | Runtime allocation | Comment | ||
---|---|---|---|---|---|
Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) | |||
Core/IOs | GPIO | GPIOA-I | ☐ | ☐ | The pins can individually be secured |
3.2.2. On STM32MP15x lines
[edit | edit source]
Click on the right to expand the legend...
Domain | Peripheral | Runtime allocation | Comment | |||
---|---|---|---|---|---|---|
Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) |
Cortex-M4 (STM32Cube) | |||
Core/IOs | GPIO | GPIOA-K | ☐ (*) | ☐ | ☐ | The pins can individually be shared (*): despite they cannot be secured, the pins can be used by the secure context |
GPIOZ | ☐ | ☐ | ☐ | The pins can individually be secured or shared |
3.2.1. On STM32MP21 unknown microprocessor device[edit | edit source]
Click on to expand or collapse the legend...
Domain | Peripheral | Runtime allocation | Comment ![]() | ||||
---|---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | |||
Core/IOs | GPIO ![]() |
GPIO | ☐ | ☐ | ☐ | ☐ | Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature |
The below table shows the possible runtime allocations for the features of the GPIO instance.
Feature | Runtime allocation ![]() |
Comment | |||
---|---|---|---|---|---|
Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | ||
GPIOA-I IOy | ☐OP-TEE ☐TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOZ IOy | ☐OP-TEE ☐TF-A BL31 |
☐ | ☐ | ☐ |
3.2.2. On STM32MP23 unknown microprocessor device[edit | edit source]
Click on to expand or collapse the legend...
Domain | Peripheral | Runtime allocation | Comment ![]() | ||||
---|---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | |||
Core/IOs | GPIO ![]() |
GPIO | ☐ | ☐ | ☐ | ☐ | Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature |
The below table shows the possible runtime allocations for the features of the GPIO instance.
Feature | Runtime allocation ![]() |
Comment | |||
---|---|---|---|---|---|
Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | ||
GPIOA-K IOy | ☐OP-TEE ☐TF-A BL31 |
☐ | ☐ | ☐ | |
GPIOZ IOy | ☐OP-TEE ☐TF-A BL31 |
☐ | ☐ | ☐ |
3.2.3. On STM32MP25 unknown microprocessor device[edit | edit source]
Click on to expand or collapse the legend...
Domain | Peripheral | Runtime allocation | Comment ![]() | |||||
---|---|---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) |
Cortex-M0+ (STM32Cube) | |||
Core/IOs | GPIO ![]() |
GPIO | ☐ | ☐ | ☐ | ☐ | ☐ | Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature |
The below table shows the possible runtime allocations for the features of the GPIO instance.
Feature | Runtime allocation ![]() |
Comment | ||||
---|---|---|---|---|---|---|
Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) |
Cortex-M0+ (STM32Cube) | ||
GPIOA-K IOy | ☐OP-TEE ☐TF-A BL31 |
☐ | ☐ | ☐ | - | |
GPIOZ IOy | ☐OP-TEE ☐TF-A BL31 |
☐ | ☐ | ☐ | ☐ |
4. Software frameworks and drivers[edit | edit source]
Below are listed the software frameworks and drivers managing the GPIO peripheral for the embedded software components listed in the above tables.
- Linux®: Linux IOs pins overview
- OP-TEE: GPIO OP-TEE driver and header file of GPIO OP-TEE driver
- STM32Cube: GPIO HAL driver and header file of GPIO HAL module
- TF-A BL2: GPIO driver and header file of GPIO driver
- U-Boot: GPIO driver and header file of GPIO driver
- TF-M: Unsupported domain! and Unsupported domain!
5. How to assign and configure the peripheral[edit | edit source]
The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:
- partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
- HAL initialization code generation for the STM32CubeMPU Package.
The configuration is applied by the firmware running in the context in which the peripheral is assigned.
In Linux kernel, each GPIO bank is declared as a "gpio-controller" in the device tree and each pin can then be used via two different consumer frameworks:
- Pinctrl framework is used to control the alternate function (AF) selection for a given device driver, via the Pinctrl device tree configuration.
- Gpiolib framework is used to control a pin in GPIO mode from another device driver or a user space application: refer to GPIO device tree configuration for further details.
6. References[edit | edit source]