USART internal peripheral

Applicable for

STM32MP13x lines, STM32MP15x lines, STM32MP21x lines, STM32MP23x lines, STM32MP25x lines

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1. Article purpose

The purpose of this article is to:

• briefly introduce the USART peripheral and its main features,
• indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
• list the software frameworks and drivers managing the peripheral,
• explain how to configure the peripheral.

2. Peripheral overview

The USART peripheral is used to interconnect STM32 MPU devices with other systems, typically via RS232 or RS485 protocols. In addition, the USART can be used for smartcard interfacing or SPI master/slave operation and supports the Synchronous mode.

The UART peripheral is similar to the USART, but does not support the Synchronous mode nor the smartcard interfacing.

High-speed data communications can be achieved by using the DMA or MDMA on STM32MP1 series and HPDMA on STM32MP2 series for multibuffer configuration.

Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.

3. Peripheral usage

This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm^® Cortex^®-A processor(s), and the STM32CubeMPU Package running on the Arm^® Cortex^®-M processor.

3.1. Boot time assignment

3.1.1. On STM32MP1 series

All USART and UART instances that are not securable via ETZPC are boot devices that support serial boot for Flash programming with STM32CubeProgrammer.

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
• ☐ means that the peripheral can be assigned to the given boot time context.
• ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
		Instance	Cortex-A7 secure (ROM code)	Cortex-A7 secure (TF-A BL2)	Cortex-A7 non-secure (U-Boot)
Low speed interface	USART	Any instance	✓	☐	☐

3.1.2. On STM32MP21x lines 

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given boot time context.
• ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
		Instance	Cortex-A35 secure (ROM code)	Cortex-A35 secure (TF-A BL2)	Cortex-A35 nonsecure (U-Boot)
Low speed interface	USART	USART1	☐	☐	☐
		USART2	☐	☐	☐
		USART3	☐	☐	☐
		UART4	☐	☐	☐
		UART5	☐	☐	☐
		USART6	☐	☐	☐
		UART7	☐	☐	☐

3.1.3. On STM32MP23x lines 

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given boot time context.
• ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
		Instance	Cortex-A35 secure (ROM code)	Cortex-A35 secure (TF-A BL2)	Cortex-A35 nonsecure (U-Boot)
Low speed interface	USART	USART1	☐	☐	☐
		USART2	☐	☐	☐
		USART3	☐	☐	☐
		UART4	☐	☐	☐
		UART5	☐	☐	☐
		USART6	☐	☐	☐
		UART7	☐	☐	☐

3.1.4. On STM32MP25x lines 

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given boot time context.
• ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
		Instance	Cortex-A35 secure (ROM code)	Cortex-A35 secure (TF-A BL2)	Cortex-A35 nonsecure (U-Boot)
Low speed interface	USART	USART1	☐	☐	☐
		USART2	☐	☐	☐
		USART3	☐	☐	☐
		UART4	☐	☐	☐
		UART5	☐	☐	☐
		USART6	☐	☐	☐
		UART7	☐	☐	☐
		UART8	☐	☐	☐
		UART9	☐	☐	☐

3.2. Runtime assignment

3.2.1. On STM32MP13x lines 

Click on to expand or collapse the legend...

STM32MP13 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
• ☐ means that the peripheral can be assigned to the given runtime context.
• ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP13 reference manuals.

Domain	Peripheral	Runtime allocation			Comment
		Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)
Low speed interface	USART	USART1	☐	☐	Assignment (single choice)
		USART2	☐	☐	Assignment (single choice)
		USART3		☐
		UART4		☐
		UART5		☐
		USART6		☐
		UART7		☐
		UART8		☐

3.2.2. On STM32MP15x lines 

Click on to expand or collapse the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
• ☐ means that the peripheral can be assigned to the given runtime context.
• ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain	Peripheral	Runtime allocation				Comment
		Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Cortex-M4 (STM32Cube)
Low speed interface	USART	USART1	☐	☐		Assignment (single choice)
		USART2		☐	☐	Assignment (single choice)
		USART3		☐	☐	Assignment (single choice)
		UART4		☐	☐	Assignment (single choice). Used for Linux® serial console on ST boards.
		UART5		☐	☐	Assignment (single choice)
		USART6		☐	☐	Assignment (single choice)
		UART7		☐	☐	Assignment (single choice)
		UART8		☐	☐	Assignment (single choice)

3.2.3. On STM32MP21x lines 

Click on to expand or collapse the legend...

STM32MP21 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given runtime context.
• ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP21 reference manuals.

Domain	Peripheral	Runtime allocation					Comment
		Instance	Cortex-A35 secure (OP-TEE / TF-A BL31)	Cortex-A35 nonsecure (Linux)	Cortex-M33 secure (TF-M)	Cortex-M33 nonsecure (STM32Cube)
Low speed interface	USART	USART1	☐OP-TEE ☐TF-A BL31	☐	☐	☐
		USART2	☐OP-TEE ☐TF-A BL31	☐	☐	☐
		USART3	☐OP-TEE ☐TF-A BL31	☐	☐	☐
		UART4	☐OP-TEE ☐TF-A BL31	☐	☐	☐
		UART5	☐OP-TEE ☐TF-A BL31	☐	☐	☐
		USART6	☐OP-TEE ☐TF-A BL31	☐	☐	☐
		UART7	☐OP-TEE ☐TF-A BL31	☐	☐	☐

3.2.4. On STM32MP23x lines 

Click on to expand or collapse the legend...

STM32MP23 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given runtime context.
• ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP23 reference manuals.

Domain	Peripheral	Runtime allocation					Comment
		Instance	Cortex-A35 secure (OP-TEE / TF-A BL31)	Cortex-A35 nonsecure (Linux)	Cortex-M33 secure (TF-M)	Cortex-M33 nonsecure (STM32Cube)
Low speed interface	USART	USART1	☐OP-TEE ☐TF-A BL31	☐	☐	☐
		USART2	☐OP-TEE ☐TF-A BL31	☐	☐	☐
		USART3	☐OP-TEE ☐TF-A BL31	☐	☐	☐
		UART4	☐OP-TEE ☐TF-A BL31	☐	☐	☐
		UART5	☐OP-TEE ☐TF-A BL31	☐	☐	☐
		USART6	☐OP-TEE ☐TF-A BL31	☐	☐	☐
		UART7	☐OP-TEE ☐TF-A BL31	☐	☐	☐

3.2.5. On STM32MP25x lines 

Click on to expand or collapse the legend...

STM32MP25 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:

• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
• ☐ means that the peripheral can be assigned to the given runtime context.
• ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.

Domain	Peripheral	Runtime allocation						Comment
		Instance	Cortex-A35 secure (OP-TEE / TF-A BL31)	Cortex-A35 nonsecure (Linux)	Cortex-M33 secure (TF-M)	Cortex-M33 nonsecure (STM32Cube)	Cortex-M0+ (STM32Cube)
Low speed interface	USART	USART1	☐OP-TEE ☐TF-A BL31	☐	☐	☐
		USART2	☐OP-TEE ☐TF-A BL31	☐	☐	☐
		USART3	☐OP-TEE ☐TF-A BL31	☐	☐	☐
		UART4	☐OP-TEE ☐TF-A BL31	☐	☐	☐
		UART5	☐OP-TEE ☐TF-A BL31	☐	☐	☐
		USART6	☐OP-TEE ☐TF-A BL31	☐	☐	☐
		UART7	☐OP-TEE ☐TF-A BL31	☐	☐	☐
		UART8	☐OP-TEE ☐TF-A BL31	☐	☐	☐
		UART9	☐OP-TEE ☐TF-A BL31	☐	☐	☐

4. Software frameworks and drivers

The STM32 MPU devices feature USART instances (supporting both Asynchronous and Synchronous modes), and UART instances (supporting only Asynchronous mode).

Below are listed the software frameworks and drivers managing the USART peripheral for the embedded software components listed in the above tables.

• Linux^®: serial/tty framework; however, the Linux^® kernel supports only the UART Asynchronous mode (Synchronous mode not supported)
• OP-TEE: USART driver and header file of USART OP-TEE driver , typically to communicate with a smartcard
• STM32Cube: USART HAL driver and header file of USART HAL module ; both USART synchronous and asynchronous modes are supported by the STM32Cube MPU Package

5. How to assign and configure the peripheral

The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:

• partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
• HAL initialization code generation for the STM32CubeMPU Package.

The configuration is applied by the firmware running in the context in which the peripheral is assigned.

See also additional information in the Serial TTY device tree configuration article for Linux^®.

6. How to go further

Additional documentation on USART peripheral is available on st.com:

• STM32 USART training presents the STM32 Universal Synchronous/Asynchronous Receiver/Transmitter interface.
• STM32 USART automatic baud rate detection presents STM32 USART automatic baud rate detection.

Universal synchronous/asynchronous receiver/transmitter

Microprocessor unit

Serial peripheral interface

Universal asynchronous receiver/transmitter

Board support package

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Extended trustzone protection controller

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