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{{ApplicableFor | |||
|MPUs list= STM32MP13x | |MPUs list=STM32MP13x | ||
|MPUs checklist=STM32MP13x, STM32MP15x | |MPUs checklist=STM32MP13x, STM32MP15x, STM32MP21x, STM32MP23x, STM32MP25x | ||
}}</noinclude> | }} | ||
This article lists all internal peripherals embedded in {{MicroprocessorDevice | device=13}} and shows the assignment possibilities to the | <noinclude></noinclude> | ||
This article lists all internal peripherals embedded in {{MicroprocessorDevice | device=13}} and shows the assignment possibilities to the execution contexts for each one of them.<br> | |||
From this article, you can also access to individual peripheral articles with information related to the overview and configuration aspects. | From this article, you can also access to individual peripheral articles with information related to the overview and configuration aspects. | ||
{{ReviewsComments|-- [[User:Jean Christophe Trotin|Jean Christophe Trotin]] ([[User talk:Jean Christophe Trotin|talk]]) 11:11, 23 November 2023 (CET)<br />Several points: | |||
* Why not writing "For the STM32CubeMP13 Package (running on the Arm<sup>®</sup> Cortex<sup>®</sup>-A7 processor), [...]" instead of "For the STM32Cube MPU package (such as e.g. STM32CubeMP13)", since the article is dedicated to the MP13 | |||
* If I correctly understand, the assignment of the peripherals is the same as the one indicated in the "OP-TEE" column. But, if, in the "OP-TEE" column, it is written that the peripherals is not assigned to the secure context (e.g. TIM 1 to 8), does it mean that there are also not assigned in the STM32CubeMP13 Package case (does it mean that there are not usable?)? | |||
* I'm wondering if the point wouldn't be to say for the STM32CubeMP13 Package that all the supported peripherals are assigned to the secure context, and it is possible to assign them to the non-secure context thanks to STM32CubeMX? <br> NSA : AP loic could you please check which of sentences proposed below illustrate in the best manner the situaiton }} | |||
{{Important| This article has be written in scope of STM32 MPU OpenSTLinux Embedded software. <br> | |||
For the STM32CubeMP13 Package (running on the Arm<sup>®</sup> Cortex<sup>®</sup>-A7 processor), the [[#Internal peripherals assignment| peripheral assignment table]] is also applicable. <br>All supported peripherals are, by default, assigned to the secure context, and it is possible to assign them to the non-secure context thanks to STM32CubeMX. <br> or <br>The default peripheral assignments for STM32CubeMP13 are described in Arm<sup>®</sup> Cortex<sup>®</sup>-A secure column of this table. As usual, the customer can change this configuration to switch in Arm<sup>®</sup> Cortex<sup>®</sup>-A non-secure context using STM32CubeMX}} | |||
{{ReviewsComments|-- [[User:Loic Pallardy|Loic Pallardy]] ([[User talk:Loic Pallardy|talk]]) 21:55, 23 November 2023 (CET)<br />agree with Jean Christophe: | |||
* need to mention Cortex-A Cube package else it could be confusing even if this page is MP13 only | |||
* in fact we should have a page that describe CA7 Cube content which allows to create a monolothic firmware running in one execution context | |||
* Cube firmware can run either on CA7 secure context or CA7 non-secure context depending on customer choice | |||
* CubeMX allows to assign/enable peripherals that will be handled by Cube firmware | |||
* so default assignment shown below is not valid, all choices are ...}} | |||
==Internal peripherals overview== | ==Internal peripherals overview== | ||
The figure below shows all '''peripherals''' embedded in | The figure below shows all '''peripherals''' embedded in {{MicroprocessorDevice | device=13}}, grouped per '''functional domains''' that are reused in many places of this wiki to structure the articles. | ||
<br /> | <br /> | ||
Several ''' | Several '''execution contexts''' exist on {{MicroprocessorDevice | device=13}}<ref>[[:Category:STM32_MPU_microprocessor_devices#Multiple-core_architecture_concepts|STM32 MPU microprocessor devices: multiple-core architecture concepts]]</ref>, corresponding to the '''Arm Cortex-A7 security modes''': | ||
* <span style="color:#FFFFFF; background:{{STPink}};"> Arm Cortex-A7 secure </span> (Trustzone), running | * <span style="color:#FFFFFF; background:{{STPink}};"> Arm Cortex-A7 secure </span> (Trustzone), running [[STM32 MPU ROM code overview|ROM code]] and [[TF-A BL2 overview|TF-A BL2]] at boot time, and running [[STM32 MPU OP-TEE overview|OP-TEE]] at runtime | ||
* <span style="color:#FFFFFF; background:{{STDarkBlue}};"> Arm Cortex-A7 non secure </span>, running [[STM32MP13 Linux kernel overview|Linux]] | * <span style="color:#FFFFFF; background:{{STDarkBlue}};"> Arm Cortex-A7 non secure </span>, running [[U-Boot overview|U-Boot]] at boot time, and running [[STM32MP13 Linux kernel overview|Linux]] at runtime | ||
Some peripherals can be strictly '''assigned''' to one | Some peripherals can be strictly '''assigned''' to one execution context, this is the case for most of the peripherals, like [[USART internal peripheral|USART]] or [[I2C internal peripheral|I2C]].<br /> | ||
Other ones can be '''shared''' between several | Other ones can be '''shared''' between several execution contexts, this is the case for system peripherals like [[STM32MP13 PWR internal peripheral|PWR]] or [[RCC internal peripheral|RCC]].<br /> | ||
The legend below shows how assigned and shared peripherals are identified in the assignment diagram that follows. | The legend below shows how assigned and shared peripherals are identified in the assignment diagram that follows. | ||
[[File: STM32MP13IPsOverview legend.png]] | [[File: STM32MP13IPsOverview legend.png]] | ||
<br /> | |||
Both the diagram below and the following summary table (in | Both the diagram below and the following summary table (in [[#Internal peripherals runtime assignment|Internal peripherals runtime assignment]] and [[#Internal peripherals boot time assignment|Internal peripherals boot time assignment]] chapters below) are clickable in order to jump to each peripheral overview article and get more detailed information (like the software frameworks used to control them). | ||
They list STMicroelectronics recommendations. The STM32MP13 reference manual <ref>[[STM32MP13 resources#Reference manuals|STM32MP13 reference manuals]]</ref> may expose more possibilities then what is shown here. | |||
{{ImageMap | Image:STM32MP13IPsOverview.png {{!}} frame {{!}} center{{!}} STM32MP13 internal peripherals overview | |||
{{ | |||
ImageMap| | |||
Image:STM32MP13IPsOverview.png {{!}} frame {{!}} center{{!}} STM32MP13 internal peripherals overview | |||
rect 15 0 176 57 [[Arm Cortex-A7 | Cortex-A7]] | rect 15 0 176 57 [[Arm Cortex-A7 | Cortex-A7]] | ||
rect 15 85 91 110 [[STGEN internal peripheral | STGEN]] | rect 15 85 91 110 [[STGEN internal peripheral | STGEN]] | ||
rect 15 116 91 141 [[ | rect 15 116 91 141 [[SYSCFG internal peripheral | SYSCFG]] | ||
rect 15 147 91 172 [[ | rect 15 147 91 172 [[RTC internal peripheral | RTC]] | ||
rect 108 85 184 110 [[EXTI internal peripheral | EXTI]] | rect 108 85 184 110 [[EXTI internal peripheral | EXTI]] | ||
rect 108 116 184 141 [[GIC internal peripheral | GIC]] | rect 108 116 184 141 [[GIC internal peripheral | GIC]] | ||
Line 45: | Line 59: | ||
rect 370 146 440 172 [[MDMA internal peripheral | MDMA]] | rect 370 146 440 172 [[MDMA internal peripheral | MDMA]] | ||
rect 712 87 787 111 [[SAES internal peripheral | SAES]] | rect 712 87 787 111 [[SAES internal peripheral | SAES]] | ||
rect 549 117 624 141 [[ | rect 549 117 624 141 [[ETZPC internal peripheral | ETZPC]] | ||
rect 630 117 706 141 [[DDRMCE internal peripheral | DDRMCE]] | rect 630 117 706 141 [[DDRMCE internal peripheral | DDRMCE]] | ||
rect 712 117 787 141 [[PKA internal peripheral | PKA]] | rect 712 117 787 141 [[PKA internal peripheral | PKA]] | ||
rect 549 147 624 172 [[TZC internal peripheral | TZC]] | rect 549 147 624 172 [[TZC internal peripheral | TZC]] | ||
rect 630 147 706 172 [[ | rect 630 147 706 172 [[RNG internal peripheral | RNG]] | ||
rect 712 147 787 172 [[ | rect 712 147 787 172 [[HASH internal peripheral | HASH]] | ||
rect 549 177 624 202 [[ | rect 549 177 624 202 [[TAMP internal peripheral | TAMP]] | ||
rect 630 177 706 202 [[CRYP internal peripheral | CRYP]] | rect 630 177 706 202 [[CRYP internal peripheral | CRYP]] | ||
rect 712 177 787 202 [[CRC internal peripheral | CRC]] | rect 712 177 787 202 [[CRC internal peripheral | CRC]] | ||
Line 67: | Line 81: | ||
rect 273 258 348 282 [[LPTIM internal peripheral | LPTIM]] | rect 273 258 348 282 [[LPTIM internal peripheral | LPTIM]] | ||
rect 439 258 515 282 [[GPIO internal peripheral | GPIO]] | rect 439 258 515 282 [[GPIO internal peripheral | GPIO]] | ||
rect 9 357 85 381 [[ | rect 9 357 85 381 [[RCC internal peripheral | RCC]] | ||
rect 9 386 85 411 [[STM32MP13 PWR internal peripheral | PWR]] | rect 9 386 85 411 [[STM32MP13 PWR internal peripheral | PWR]] | ||
rect 9 416 85 440 [[DTS internal peripheral | DTS]] | rect 9 416 85 440 [[DTS internal peripheral | DTS]] | ||
Line 98: | Line 112: | ||
}} | }} | ||
==Internal peripherals assignment== | ==Internal peripherals runtime assignment== | ||
{{: | {{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp13_runtime}} | ||
{{:STM32MP13_ADC_internal_peripheral}} | {{#lst:STM32MP13_ADC_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:DFSDM_internal_peripheral| | {{#lst:DFSDM_internal_peripheral|stm32mp13_runtime}} | ||
{{:STM32MP13_VREFBUF_internal_peripheral}} | {{#lst:STM32MP13_VREFBUF_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:SAI internal peripheral| | {{#lst:SAI internal peripheral|stm32mp13_runtime}} | ||
{{#lst:SPDIFRX_internal_peripheral| | {{#lst:SPDIFRX_internal_peripheral|stm32mp13_runtime}} | ||
{{: | {{#lst:RTC_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:STGEN_internal_peripheral| | {{#lst:STGEN_internal_peripheral|stm32mp13_runtime}} | ||
{{: | {{#lst:SYSCFG_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:DMA_internal_peripheral| | {{#lst:DMA_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:DMAMUX_internal_peripheral| | {{#lst:DMAMUX_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:MDMA_internal_peripheral| | {{#lst:MDMA_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:EXTI_internal_peripheral| | {{#lst:EXTI_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:GIC_internal_peripheral| | {{#lst:GIC_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:GPIO internal peripheral| | {{#lst:GPIO internal peripheral|stm32mp13_runtime}} | ||
{{#lst:BKPSRAM internal memory| | {{#lst:BKPSRAM internal memory|stm32mp13_runtime}} | ||
{{#lst:DDRCTRL and DDRPHYC internal peripherals| | {{#lst:DDRCTRL and DDRPHYC internal peripherals|stm32mp13_runtime}} | ||
{{:STM32MP13 SRAM internal memory}} | {{#lst:STM32MP13 SRAM internal memory|stm32mp13_runtime}} | ||
{{#lst:SYSRAM_internal_memory| | {{#lst:SYSRAM_internal_memory|stm32mp13_runtime}} | ||
{{#lst:LPTIM_internal_peripheral| | {{#lst:LPTIM_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:TIM_internal_peripheral| | {{#lst:TIM_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:IWDG_internal_peripheral| | {{#lst:IWDG_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:OTG_internal_peripheral| | {{#lst:OTG_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:USBH_internal_peripheral| | {{#lst:USBH_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:USBPHYC internal peripheral| | {{#lst:USBPHYC internal peripheral|stm32mp13_runtime}} | ||
{{#lst:I2C_internal_peripheral| | {{#lst:I2C_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:SPI_internal_peripheral| | {{#lst:SPI_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:USART_internal_peripheral| | {{#lst:USART_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:FMC internal peripheral| | {{#lst:FMC internal peripheral|stm32mp13_runtime}} | ||
{{#lst:QUADSPI internal peripheral| | {{#lst:QUADSPI internal peripheral|stm32mp13_runtime}} | ||
{{#lst:SDMMC internal peripheral| | {{#lst:SDMMC internal peripheral|stm32mp13_runtime}} | ||
{{#lst:ETH internal peripheral| | {{#lst:ETH internal peripheral|stm32mp13_runtime}} | ||
{{#lst:FDCAN internal peripheral| | {{#lst:FDCAN internal peripheral|stm32mp13_runtime}} | ||
{{#lst:DTS_internal_peripheral| | {{#lst:DTS_internal_peripheral|stm32mp13_runtime}} | ||
{{:STM32MP13_PWR_internal_peripheral}} | {{#lst:STM32MP13_PWR_internal_peripheral|stm32mp13_runtime}} | ||
{{: | {{#lst:RCC_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:BSEC_internal_peripheral| | {{#lst:BSEC_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:CRC_internal_peripheral| | {{#lst:CRC_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:CRYP_internal_peripheral| | {{#lst:CRYP_internal_peripheral|stm32mp13_runtime}} | ||
{{: | {{#lst:ETZPC_internal_peripheral|stm32mp13_runtime}} | ||
{{: | {{#lst:HASH_internal_peripheral|stm32mp13_runtime}} | ||
{{:DDRMCE_internal_peripheral}} | {{#lst:DDRMCE_internal_peripheral|stm32mp13_runtime}} | ||
{{:PKA_internal_peripheral}} | {{#lst:PKA_internal_peripheral|stm32mp13_runtime}} | ||
{{: | {{#lst:RNG_internal_peripheral|stm32mp13_runtime}} | ||
{{:SAES_internal_peripheral}} | {{#lst:SAES_internal_peripheral|stm32mp13_runtime}} | ||
{{: | {{#lst:TAMP_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:TZC_internal_peripheral| | {{#lst:TZC_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:DBGMCU_internal_peripheral| | {{#lst:DBGMCU_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:DDRPERFM_internal_peripheral| | {{#lst:DDRPERFM_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:HDP_internal_peripheral| | {{#lst:HDP_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst: | {{#lst:DCMIPP_internal_peripheral|stm32mp13_runtime}} | ||
{{:DCMIPP_internal_peripheral}} | {{#lst:LTDC_internal_peripheral|stm32mp13_runtime}} | ||
{{#lst:LTDC_internal_peripheral| | |} | ||
==Internal peripherals boot time assignment== | |||
{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp1_boottime}} | |||
{{#lst:STM32MP13_ADC_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:DFSDM_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:STM32MP13_VREFBUF_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:SAI internal peripheral|stm32mp13_boottime}} | |||
{{#lst:SPDIFRX_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:RTC_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:STGEN_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:SYSCFG_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:DMA_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:DMAMUX_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:MDMA_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:EXTI_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:GIC_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:GPIO internal peripheral|stm32mp13_boottime}} | |||
{{#lst:BKPSRAM internal memory|stm32mp13_boottime}} | |||
{{#lst:DDRCTRL and DDRPHYC internal peripherals|stm32mp13_boottime}} | |||
{{#lst:STM32MP13 SRAM internal memory|stm32mp13_boottime}} | |||
{{#lst:SYSRAM_internal_memory|stm32mp13_boottime}} | |||
{{#lst:LPTIM_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:TIM_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:IWDG_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:OTG_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:USBH_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:USBPHYC internal peripheral|stm32mp13_boottime}} | |||
{{#lst:I2C_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:SPI_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:USART_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:FMC internal peripheral|stm32mp13_boottime}} | |||
{{#lst:QUADSPI internal peripheral|stm32mp13_boottime}} | |||
{{#lst:SDMMC internal peripheral|stm32mp13_boottime}} | |||
{{#lst:ETH internal peripheral|stm32mp13_boottime}} | |||
{{#lst:FDCAN internal peripheral|stm32mp13_boottime}} | |||
{{#lst:DTS_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:STM32MP13_PWR_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:RCC_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:BSEC_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:CRC_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:CRYP_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:ETZPC_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:HASH_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:DDRMCE_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:PKA_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:RNG_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:SAES_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:TAMP_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:TZC_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:DBGMCU_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:DDRPERFM_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:HDP_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:DCMIPP_internal_peripheral|stm32mp13_boottime}} | |||
{{#lst:LTDC_internal_peripheral|stm32mp13_boottime}} | |||
|} | |} | ||
Latest revision as of 16:19, 7 October 2024
This article lists all internal peripherals embedded in STM32MP13x lines and shows the assignment possibilities to the execution contexts for each one of them.
From this article, you can also access to individual peripheral articles with information related to the overview and configuration aspects.
1. Internal peripherals overview[edit | edit source]
The figure below shows all peripherals embedded in STM32MP13x lines , grouped per functional domains that are reused in many places of this wiki to structure the articles.
Several execution contexts exist on STM32MP13x lines [1], corresponding to the Arm Cortex-A7 security modes:
- Arm Cortex-A7 secure (Trustzone), running ROM code and TF-A BL2 at boot time, and running OP-TEE at runtime
- Arm Cortex-A7 non secure , running U-Boot at boot time, and running Linux at runtime
Some peripherals can be strictly assigned to one execution context, this is the case for most of the peripherals, like USART or I2C.
Other ones can be shared between several execution contexts, this is the case for system peripherals like PWR or RCC.
The legend below shows how assigned and shared peripherals are identified in the assignment diagram that follows.
Both the diagram below and the following summary table (in Internal peripherals runtime assignment and Internal peripherals boot time assignment chapters below) are clickable in order to jump to each peripheral overview article and get more detailed information (like the software frameworks used to control them). They list STMicroelectronics recommendations. The STM32MP13 reference manual [2] may expose more possibilities then what is shown here.

2. Internal peripherals runtime assignment[edit | edit source]
Click on to expand or collapse the legend...
Check boxes illustrate the possible peripheral allocations supported by the OpenSTLinux BSP:
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
- ☐ means that the peripheral can be assigned to the given runtime context.
- ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP13 reference manuals.
Domain | Peripheral | Runtime allocation | Comment ![]() | ||
---|---|---|---|---|---|
Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 nonsecure (Linux) | |||
Core | RTC | RTC | ☑ | ☐ | RTC is mandatory to resynchronize STGEN after exiting low-power modes. |
Core | SYSCFG | SYSCFG | ☑ | ☑ | |
Power & Thermal | RCC | RCC | ✓ | ✓ | |
Security | ETZPC | ETZPC | ✓ | ✓ | |
Security | HASH | HASH | ☐ | ☐ | Assignment (single choice) |
Security | RNG | RNG | ☐ | ☐ | Assignment (single choice) |
Security | TAMP | TAMP | ☑ | ☑ |
3. Internal peripherals boot time assignment[edit | edit source]
Click on to expand or collapse the legend...
Check boxes illustrate the possible peripheral allocations supported by the OpenSTLinux BSP:
- ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
- ☐ means that the peripheral can be assigned to the given boot time context.
- ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.
Domain | Peripheral | Boot time allocation | Comment ![]() | |||
---|---|---|---|---|---|---|
Instance | Cortex-A7 secure (ROM code) |
Cortex-A7 secure (TF-A BL2) |
Cortex-A7 nonsecure (U-Boot) | |||
Core | RTC | RTC | ☐ | |||
Core | SYSCFG | SYSCFG | ✓ | ☑ | ☑ | |
Power & Thermal | RCC | RCC | ✓ | ✓ | ✓ | |
Security | ETZPC | Any instance | ✓ | ✓ | ✓ | ETZPC configuration is set by OP-TEE |
Security | HASH | HASH | ✓ | ☑ | ||
Security | RNG | RNG | ✓ | ☑ | ☐ | Required for DPA peripheral protection |
Security | TAMP | TAMP | ✓ | ☑ | ☑ |
4. References[edit | edit source]