1. Article purpose[edit | edit source]
The purpose of this article is to:
- briefly introduce the Arm® Cortex®-M0+ (coprocessor) peripheral and its main features,
- indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
- list the software frameworks and drivers managing the peripheral,
- explain how to configure the peripheral.
2. Peripheral overview[edit | edit source]
The Arm® Cortex®-M0+ (coprocessor) Arm® is a Armv6-M 32-bit processor. It is a very energy efficient processor dedicated to low power use cases. Among a wide range of features, it includes:
- a 2-stage pipeline,
- a memory protection unit (MPU),
- Non-Maskable Interrupt (NMI),
- Serial Wire Debug.
The Cortex-M0+ supports only a non-secure mode that define one hardware execution contexts, named Cortex-M0+ non-secure.
The Cortex-M0+ is present in the STM32MP25x lines 
, integrated in a dedicated power domain named D3.
Its main usage is low power batch acquisition mode with Cortex-A35 and Cortex-M33 in low power mode or power off.
The Cortex-M0+ can be controlled either by Cortex-A35 or by Cortex-M33. Once loaded and started, Cortex-M0+ can run independently from rest of the system.
Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented in the STM32MPU Embedded Software distribution.
3. Peripheral usage[edit | edit source]
This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm® Cortex®-A processor(s), and the STM32CubeMPU Package running on the Arm® Cortex®-M processor.
3.1. Boot time assignment[edit | edit source]
3.1.1. On STM32MP25x lines [edit | edit source]
Click on 
to expand or collapse the legend...
Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:
- ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
- ☐ means that the peripheral can be assigned to the given boot time context.
- ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.
| Domain | Peripheral | Boot time allocation | Comment
| |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | |||
| Core/Processors | Arm® Cortex®-M0+ (coprocessor) | Arm® Cortex®-M0+ | ⬚ | ⬚ | ||
3.2. Runtime assignment[edit | edit source]
3.2.1. On STM32MP25x lines [edit | edit source]
Click on to expand or collapse the legend...
Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
- ☐ means that the peripheral can be assigned to the given runtime context.
- ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment
| |||||
|---|---|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) |
Cortex-M0+ (STM32Cube) | |||
| Core/Processors | Arm® Cortex®-M0+ (coprocessor) | Arm® Cortex®-M0+ (coprocessor) | ⬚OP-TEE | ☐ | ⬚ | ⬚ | ||
4. Software frameworks and drivers[edit | edit source]
Below are listed the software frameworks and drivers managing the Arm® Cortex®-M0+ (coprocessor) for the embedded software components listed in the above tables.
- The Cortex-M0+ runs applications developed using to the STM32CubeMP2 distribution package.
- The Cortex-M0+ can be startup at runtime, with or without firmware authentication, using the remoteproc frameworks available in different components of the OpenSTLinux distribution:
- Linux®: Linux remoteproc framework
- The Cortex-M0+ operates as a coprocessor, either autonomously as any external microcontroller, or communicating with the other processors (Cortex-A35 or Cortex-M33) via the IPCC.
5. How to assign and configure the peripheral[edit | edit source]
The Cortex-M0+ assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure two aspects:
- Which Cortex-A35 or Cortex-M33 SW component is in charge of Cortex-M0+ management
- Which peripherals are assigned to Cortex-M0+
CubeMX allows generating:
- partial device trees (pin control and clock tree and firewall configuration) for the OpenSTLinux software components,
- HAL initialization code for the STM32CubeMPU Package.
The configuration is applied by the firmware running in the context in which the peripheral is assigned.
6. How to go further[edit | edit source]
Refer to the Arm website[1] for more detailed information on this core.
Refer to the How to use the Cortex-M0+ page for an example of the Cortex-M0+ usage in the STM32MPU Embedded Software distribution.
7. References[edit | edit source]
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.