1. Article purpose[edit | edit source]
The purpose of this article is to:
- briefly introduce the Arm® Cortex®-M33 (coprocessor) and its main features,
- indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
- list the software frameworks and drivers managing the peripheral,
- explain how to configure the peripheral.
2. Peripheral overview[edit | edit source]
The Arm® Cortex®-M33 (coprocessor) Arm® is a Armv8-M 32-bit processor. Among a wide range of features, it includes:
- a memory protection unit (MPU)
- a single-precision floating point unit (FPU)
- a DSP extension
- TrustZone security
The Cortex-M33 supports a non-secure mode and a secure mode thanks to TrustZone that define two hardware execution contexts, named Cortex-M33 non-secure and Cortex-M33 secure.
The Cortex-M33 is present across all the STM32MP2 series. In Cortex-A35 main processor mode, the Cortex-M33 is seen as a coprocessor controlled by Cortex-A35. In Cortex-M33 main processor mode, the Cortex-M33 is directly started by the ROM code after a power on reset. It is the principal processor and doesn't depend on the Cortex-A35 for its execution.
Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.
3. Peripheral usage[edit | edit source]
This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm® Cortex®-A processor(s), and the STM32CubeMPU Package running on the Arm® Cortex®-M processor.
3.1. Boot time assignment[edit | edit source]
The Cortex-M33 can be startup at boot time by U-Boot SSBL (see boot chain) , as explained in the How to start the coprocessor from the bootloader article.
Thanks to a specific OP-TEE trusted application (TA) running on the Arm® TrustZone and to the Resource Isolation Framework, it is possible to authenticate the Cortex®-M33 firmware and install it on isolated memory region to ensure its integrity during the execution. For details, please refer to How_to_protect_the_coprocessor_firmware article.
3.1.1. On STM32MP2 series[edit | edit source]
Click on 
to expand or collapse the legend...
Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:
- ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in OpenSTLinux BSP.
- ☐ means that the peripheral can be assigned to the given boot time context.
- ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the OpenSTLinux BSP.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.
| Domain | Peripheral | Boot time allocation | Comment
| |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 nonsecure (U-Boot) | |||
| Core/Processors | Arm® Cortex®-M33 (coprocessor) | Arm® Cortex®-M33 (coprocessor) | ⬚ | ☐ | How to start the coprocessor from the bootloader How_to_protect_the_coprocessor_firmware | |
3.2. Runtime assignment[edit | edit source]
The Cortex-M33 can be started and stopped at runtime by the Linux remoteproc framework.
Thanks to a specific OP-TEE trusted application (TA) running on the Arm® TrustZone and to the ETZPC peripheral, it is possible to authenticate the Cortex-M33 firmware and to install it on isolated memory region to ensure its integrity during the execution. For details, please refer to How_to_protect_the_coprocessor_firmware article.
Once started, the Cortex-M33 executes the STM32CubeMP2 firmware, which controls the Cortex-M33 internal resources (MPU, WFI,...)
3.2.1. On STM32MP21x lines 
[edit | edit source]
Click on to expand or collapse the legend...
Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
- ☐ means that the peripheral can be assigned to the given runtime context.
- ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP21 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment
| ||||
|---|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | |||
| Core/Processors | Arm® Cortex®-M33 (coprocessor) | Arm® Cortex®-M33 (coprocessor) | ☐OP-TEE | ☐ | ☐ | ✓ | Controlled by LInux or OP-TEE. Running the STM32CubeMP2 firmware. |
3.2.2. On STM32MP23x lines [edit | edit source]
Click on to expand or collapse the legend...
Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
- ☐ means that the peripheral can be assigned to the given runtime context.
- ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP23 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment
| ||||
|---|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) | |||
| Core/Processors | Arm® Cortex®-M33 (coprocessor) | Arm® Cortex®-M33 (coprocessor) | ☐OP-TEE | ☐ | ☐ | ✓ | Controlled by LInux or OP-TEE. Running the STM32CubeMP2 firmware. |
3.2.3. On STM32MP25x lines [edit | edit source]
Click on to expand or collapse the legend...
Check boxes illustrate the possible peripheral allocations supported by OpenSTLinux BSP:
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in OpenSTLinux BSP.
- ☐ means that the peripheral can be assigned to the given runtime context.
- ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the OpenSTLinux BSP.
- ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.
Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment
| |||||
|---|---|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 nonsecure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 nonsecure (STM32Cube) |
Cortex-M0+ (STM32Cube) | |||
| Core/Processors | Arm® Cortex®-M33 (coprocessor) | Arm® Cortex®-M33 (coprocessor) | ☐OP-TEE | ☐ | ☐ | ✓ | Controlled by LInux or OP-TEE. Running the STM32CubeMP2 firmware. | |
4. Software frameworks and drivers[edit | edit source]
Below are listed the software frameworks and drivers managing the Arm® Cortex®-M33 (coprocessor) for the embedded software components listed in the above tables.
- The Cortex-M33 runs applications developed using to the STM32CubeMP2 distribution package.
- STM32CubeMP2 distribution package could be associated to TF-M for security services management.
- The Cortex-M33 can be startup at boot time or at runtime, with or without firmware authentication, using the remoteproc frameworks available in different components of the OpenSTLinux distribution:
- Linux®: Linux remoteproc framework
- U-Boot: drivers/remoteproc
- OP-TEE: OP-TEE remoteproc source code
- The Cortex-M33 operates as a coprocessor, either autonomously as any external microcontroller, or communicating with the main processor (Cortex-A35) via the RPMsg communication pipe.
5. How to assign and configure the peripheral[edit | edit source]
The Cortex-M33 assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure two aspects:
- Which Cortex-A35 SW component is in charge of Cortex-M33 management
- Which peripherals are assigned to Cortex-M33
CubeMX allows generating:
- partial device trees (pin control and clock tree and firewall configuration) for the OpenSTLinux software components,
- HAL initialization code for the STM32CubeMPU Package.
The configuration is applied by the firmware running in the context in which the peripheral is assigned.
6. How to go further[edit | edit source]
Refer to the Arm website[1] for more detailed information on this core.
7. References[edit | edit source]
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.