SAES internal peripheral

Applicable for

STM32MP13x lines

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1. Article purpose

The purpose of this article is to:

• briefly introduce the SAES peripheral and its main features
• indicate the level of security supported by this hardware block
• explain how it can be allocated to the runtime contexts and linked to the corresponding software components
• explain, when necessary, how to configure the SAES peripheral.

2. Peripheral overview

The SAES peripheral provides hardware acceleration to encrypt or decrypt data using the AES algorithms. It supports 2 key sizes (128 and 256 bits) and different chaining modes. It incorporates protections against differential power analysis (DPA) and related side-channel attacks.

2.1. Features

Refer to the STM32MP13 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

• It supports for cipher key lengths of 128-bit and 256-bit
• It supports the follwing chaining mode:
  • Electronic codebook (ECB) mode
  • Cipher block chaining (CBC) mode
  • Counter (CTR) mode
  • Galois counter mode (GCM)
  • Galois message authentication code (GMAC) mode
  • Counter with CBC-MAC (CCM) mode
• It support different key management
  • 256-bit write-only register for storing the cryptographic key (eight 32-bit registers)
  • Hardware loading of two hardware secret keys (BHK, DHUK) that can be XOR-ed together
• It support single-transfer direct memory access (DMA) using two channels (one for incoming data, one for processed data)
• It supports data-swapping logic to support 1-, 8-, 16- or 32-bit data
• It support to suspend a message if SAES needs to process another message with a higher priority, then resume the original message
• It support security context enforcement for keys
• It can encrypt/decrypt Hardware secret key (Wrapped-key mode)
• It is Protected against side-channel attacks (SCA), incl. differential power analysis (DPA)
• It can share key with faster CRYP peripheral (Shared-key mode), controlled by SAES

2.2. Security support

The SAES is a mixed non-secure and secure peripheral (under ETZPC control): If KEY_PROTECT bit is set, keys are reset if a new access is done from the other side. Or if KEY_PROTECT is not set, key can be set from secured world then use in non secure world (and key stay not directly readable)

3. Peripheral usage and associated software

3.1. Boot time

The SAES instance is a boot devices that decrypts (possibly) crypted bootloaders.

3.2. Runtime

3.2.1. Overview

SAES instance can be allocated to:

• the Arm^® Cortex^®-A7 secure core to be controlled in OP-TEE by the SAES OP-TEE driver through the CIPHER framework and AUTHENC framework.

or

• the Arm^® Cortex^®-A7 non-secure core to be controlled in Linux^® by a SAES driver (not yet implemented)

Chapter Peripheral assignment describes which peripheral instance can be assigned to which context.

3.2.2. Software frameworks

Domain	Peripheral	Software components		Comment
		OP-TEE	Linux
Domain	SAES	OP-TEE SAES driver	Linux cipher framework

3.2.3. Peripheral configuration

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.

3.2.4. Peripheral assignment

Click on the right to expand the legend...

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

• ☐ means that the peripheral can be assigned (☑) to the given runtime context.
• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
• ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

Domain	Peripheral	Runtime allocation			Comment
		Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)
Security	SAES	SAES	☐	⬚	Assignment (single choice)

Advanced encryption standard

Differential power analysis

Direct memory access

Cryptographic processor

Arm^® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Cortex^®

Open portable trusted execution environment

Linux^® is a registered trademark of Linus Torvalds.