Last edited one year ago

Arm CoreSight overview

Applicable for STM32MP13x lines, STM32MP15x lines

1. Article purpose[edit source]

The purpose of this article is to provide information on the Arm® CoreSight hardware subsystem.
It explains what are the principle peripherals of this subsystem.

2. Peripheral overview[edit source]

Arm® CoreSight products include

  • a wide range of trace macrocells for Arm® processors,

To enable the debug and trace of the most complex, multi-core SoCs, Arm® CoreSight products include

  • a system and software instrumentation,
  • and a comprehensive set of IP blocks.

Arm® has defined an open CoreSight architecture to allow SoC designers to add "debug and trace" capabilities for other IP cores in to the CoreSight infrastructure.

Alternate text
CoreSight overview of STM32MP15. Check the Reference Manual for the other devices

2.1. Components description[edit source]

The debug features are based on Arm® CoreSight™ components

Arm® CoreSight™ components STM32MP13x lines More info.png STM32MP15x lines More info.png
SWJ-DP: JTAG/Serial-wire debug port Yes Yes
AXI-AP: AXI access port Yes Yes
AHB-AP: AHB access port No Yes
APB-AP: APB access port Yes Yes
ITM: Instrumentation Trace Macrocell No Yes
DWT: Data Watchpoint and Trace No Yes
FPB: Flash Patch and Breakpoint No Yes
ETM: Embedded Trace Macrocell Yes Yes
ETF: Embedded Trace FIFO Yes Yes
TPIU: Trace Port Interface Unit Yes Yes
SWO: Serial Wire Output No Yes
CTI: Cross Trigger Interface Yes Yes
CTM: Cross Trigger Matrix Yes Yes
TSGEN: Timestamp Generator Yes Yes
STM: System Trace Macrocell No Yes

More information about these components can be found in the Arm® website [1]

2.2. Features[edit source]

Refer to the Debug support (DBG) chapter of reference manuals corresponding to the STM32 MPU, you use, for the complete list of features, and to the software components, introduced above, to see which features are really implemented.

3. References[edit source]