BootRom for STM32N6

The ROM code is the first code executed by the Arm® Cortex®-M55 core(s) after system reset.

The boot ROM code is the initial code executed on Arm® Cortex®-M55 at power-on or reset of the STM32N6 MCU or Arm® Cortex®-M55. This boot ROM code resides in the STM32N6 on-chip boot ROM IP and implements the first stage of a multistage boot sequence.

The main boot ROM code features and functions are:

  • Basic system initialization
  • Detection of reset source and chip life cycle
  • Handling life cycle
  • Loading image from a connected flash memory device supporting various types of memory devices
  • Downloading image from a host over serial boot interfaces
  • Validation of signed images using hardware accelerators for cryptographic functions
  • Optional decryption of signed images
  • Support of developer mode
  • Support of configuration options (customization), mainly via fuses
  • Support of ST key provisioning
  • Support of SSP, OEM key provisioning

The table below details the possible options for some of these features.

Image loading Supported flash memories XSPI serial NOR

XSPI Hyperflash

eMMC (up to JEDEC v5.1) on SDMMC1 or SDMMC2

SD-Card (up to SD standard v6.0) on SDMMC1

Supported serial interfaces and protocols

USB : USB DFU 1.1 on USB 2.0 OTG HS

UART: STM32 serial protocol on USART1, USART2, UART4

STM32 header v2.3
Image max size (with STM32 header) 512 KB
Secure boot FSBL authentication ECDSA 256 or 384 bits
Revocation of FSBL authentication key Up to 8 keys
FSBL anti-rollback mechanism Up to 32 versions
FSBL decryption AES 128 or 256 bits


For full details, please refer to the User Manual : DM01007578 - UM3234 - "How to proceed with boot ROM on STM32N6 MCUs".