STM32MP25 LPSRAM internal memory

Applicable for

1. Article purpose[edit | edit source]

The purpose of this article is to:

briefly introduce the LPSRAM internal memory peripheral and its main features,
indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
list the software frameworks and drivers managing the peripheral,
explain how to configure the peripheral.

2. Peripheral overview[edit | edit source]

The LPSRAM peripheral is low power SRAM physically near to the Cortex-M0+ for optimized low power batch acquisition applications. It is split into three separate banks:

LPSRAM1 (8 Kbytes): dedicated to Cortex-M0+ code, protected by CRC to guarantee code integrity in low power mode exit. This bank could be preserved in low power Standby mode,
LPSRAM2 (8 Kbytes): dedicated to Cortex-M0+ firmware data/stack,
LPSRAM3 (16 Kbytes): used for data acquisition and sharing with Cortex-A35 and/or Cortex-M33.

Each bank is protected via a RISAL memory firewall allowing to define memory regions with different access rights. Each region could be assigned to or shared between different execution contexts. Each bank also owns automatic clock gating (for power management optimization) which can be linked:

either on one processor low power state if the bank is only assigned to this processor,
or on system low power state if the bank is assigned to several processors.

Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.

3. Peripheral usage[edit | edit source]

This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm Cortex-A processor(s), and the STM32CubeMPU Package running on the Arm Cortex-M processor.

3.1. Boot time assignment[edit | edit source]

3.1.1. On STM32MP2 series[edit | edit source]

LPSRAM banks are not used at boot time.

Click on to expand or collapse the legend...

⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
☐ means that the peripheral can be assigned to the given boot time context.
☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.

Domain	Peripheral	Boot time allocation				Comment
Domain	Peripheral	Instance	Cortex-A35 secure (ROM code)	Cortex-A35 secure (TF-A BL2)	Cortex-A35 non-secure (U-Boot)	Comment
Core/RAM	LPSRAM	LPSRAM1
		LPSRAM2
		LPSRAM3

3.2. Runtime assignment[edit | edit source]

3.2.1. On STM32MP25x lines [edit | edit source]

At runtime, the LPSRAM1 and LPSRAM2 could be used by the Cortex-M0+ to execute a small firmware dedicated to some low power batch acquisition applications.

As Cortex-M0+ could be controlled as a coprocessor by Cortex-A35 or Cortex-M33, LPSRAM1 and LPSRAM2 should also be accessible by the processor controlling the Cortex-M0+ during its initialization sequence.

The LPSRAM3 is mainly dedicated to the data acquisition. It is in general shared between the Cortex-M0+ and the processor controlling it.

Click on to expand or collapse the legend...

STM32MP25 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
☐ means that the peripheral can be assigned to the given runtime context.
☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.

Domain	Peripheral	Runtime allocation						Comment
Domain	Peripheral	Instance	Cortex-A35 secure (OP-TEE / TF-A BL31)	Cortex-A35 non-secure (Linux)	Cortex-M33 secure (TF-M)	Cortex-M33 non-secure (STM32Cube)	Cortex-M0+ (STM32Cube)	Comment
Core/RAM	LPSRAM	LPSRAM1	☐^OP-TEE ☐^BL31	☐	☐	☐	☑	Should contain Cortex-M0+ firmware code
		LPSRAM2	☐^OP-TEE ☐^BL31	☐	☐	☐	☑	Should contain Cortex-M0+ firmware data
		LPSRAM3	☐^OP-TEE ☐^BL31	☐	☐	☐	☑

4. Software frameworks and drivers[edit | edit source]

Below are listed the software frameworks and drivers using the LPSRAM peripheral for the embedded software components listed in the above tables.

Linux: reserved memory, that is used by the dmaengine (for DMA buffers management) or RPMsg for interprocess communication with the coprocessor
OP-TEE: OP-TEE
STM32Cube: STM32Cube
TF-M: TF-M

The default assignment set in STMicroelectronics distribution is in line with the platform memory mapping, that can be adapted by the platform user.

5. How to assign and configure the peripheral[edit | edit source]

The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:

partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
HAL initialization code generation for the STM32CubeMPU Package.

The configuration is applied by the firmware running in the context in which the peripheral is assigned.