1. Article purpose[edit | edit source]
This article explains how to configure the HPDMA internal peripheral when it is assigned to the Linux® OS. In that case, it is controlled by the DMA Engine (Refer to Dmaengine overview).
The configuration is performed using the Device tree mechanism that provides a hardware description of the HPDMA internal peripheral, used by the STM32 DMA3 Linux driver and by the DMA framework.
Hardware description is a combination of:
- STM32 HPDMA peripheral,
- STM32 HPDMA client.
2. DT bindings documentation[edit | edit source]
Complete device tree bindings can be found at this location: [1]
3. DT configuration[edit | edit source]
This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the Device tree for an explanation of the device tree file split.
STM32CubeMX can be used to generate the board device tree. Refer to How to configure the DT using STM32CubeMX for more details.
3.1. DT configuration (STM32 level)[edit | edit source]
The STM32MP2 HPDMA node for STM32MP25x lines 
is located in stm32mp251.dtsi[2]
For example, at device level, the HPDMA is declared as follows:
hpdma: dma-controller@40400000 {
compatible = "st,stm32-dma3";
reg = <0x40400000 0x1000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk CK_SCMI_HPDMA1>;
power-domains = <&RET_PD>;
#dma-cells = <3>;
st,axi-max-burst-len = <16>;
};
3.2. DT configuration (board level)[edit | edit source]
Board device tree configuration can be used to specify memory-region property pointing on reserved memory used for HPDMA internal descriptors.
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
[...]
hpdma1_lli: hpdma1-lli@a020000 {
reg = <0x0 0xa020000 0x0 0xf0f0>;
no-map;
};
[...]
};
&hpdma {
memory-region = <&hpdma1_lli>;
};
3.2.1. DT configuration of HPDMA channels assignment[edit | edit source]
HPDMA is a RIF-aware peripheral and it is possible to assign HPDMA channels to different execution contexts.
HPDMA RIF configuration must be done by the Secure OS of the main processor (TDCID).
A specific binding is used in OP-TEE device tree to set RIF configuration at boot time, by defining the st,protreg property. It is defined at board level:
&hpdma3 {
--> configure RIFSC for HPDMA3 channels 0 to 13 assigned to CID2 and channels 14 to 15 assigned to CID1, all non secure and privileged
st,protreg = <
RIFPROT(RIF_HPDMA_CHANNEL(0), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN)
RIFPROT(RIF_HPDMA_CHANNEL(1), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN)
[...]
RIFPROT(RIF_HPDMA_CHANNEL(11), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN)
RIFPROT(RIF_HPDMA_CHANNEL(12), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN)
RIFPROT(RIF_HPDMA_CHANNEL(13), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN)
RIFPROT(RIF_HPDMA_CHANNEL(14), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
RIFPROT(RIF_HPDMA_CHANNEL(15), RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
>;
};
Where:
- - hpdma3: phandle on dma-controller node.
- - RIFPROT: Macro use to configure RIFSC. See RIFSC device tree bindings RIFSC bindings for more information.
3.3. DT configuration examples[edit | edit source]
HPDMA mappings (client request line and client channel/transfer requirements) are defined in the consumer device node, through a property named dmas. Refer to How to request a DMA channel.
The example below shows how to map a channel to DMA request line 73 (sai1_a) to sai1a device:
sai1a: audio-controller@40290004 {
[...]
dmas = <&hpdma 73 0x43 0x21>;
[...]
};
Where (see HPDMA device tree bindings HPDMA bindings ):
- - &hpdma: phandle on first dma-controller node.
- - 73: dma request line in dma-controller. Refer to the STM32MP25xx reference manual, HPDMA requests chapter, for the HPDMA requests mapping.
- - 0x43: dma channel requirements, where bit[7:4] (FIFO requirement), 4 -> 24+1= FIFO of 32 bytes. A channel with FIFO of 32 bytes has to be found in Medium performance group channels, aka channels with index between 8 to 11. Refer to HPDMA internal peripheral.
- - 0x21: dma transfer requirements.
4. How to configure the DT using STM32CubeMX[edit | edit source]
The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.
The STM32CubeMX may not support all the properties described in the above DT bindings documentation paragraph. If so, the tool inserts user sections in the generated device tree. These sections can then be edited to add some properties and they are preserved from one generation to another. Refer to STM32CubeMX user manual for further information.
5. References[edit | edit source]
Please refer to the following links for additional information: