1. Article purpose[edit | edit source]
The purpose of this article is to:
- briefly introduce the DDRMCE peripheral and its main features,
- indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
- list the software frameworks and drivers managing the peripheral,
- explain how to configure the peripheral.
2. Peripheral overview[edit | edit source]
The DDRMCE (DDR Memory Cipher Engine) peripheral allows to define one AES encrypted region in DDR memory.
 Information
|
| Functions and registers names declared in the embedded software are using "MCE" / "mce" acronym instead of the longest "DDRMCE" / "ddrmce" ones, so take care about this for any research in the code. |
The DDRMCE 128-bit master key is provisioned during boot processing, in order to use AES[1] block ciphering feature. It must be fully saved in BKPSRAM for low power sequences.
Refer to the STM32MP13 reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.
3. Peripheral usage[edit | edit source]
This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm® Cortex®-A processor(s), and the STM32CubeMPU Package running on the Arm® Cortex®-M processor.
3.1. Boot time assignment[edit | edit source]
3.1.1. On STM32MP13x lines 
[edit | edit source]
The DDRMCE peripheral, part of the DDR subsystem, is configured inside TF-A BL2 to setup the security of a DDR region thanks to TF-A FW Configuration. This should be done before accessing DDR region if encryption is required.
Click on 
to expand or collapse the legend...
| Domain | Peripheral | Boot time allocation | Comment
| |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (ROM code) |
Cortex-A7 secure (TF-A BL2) |
Cortex-A7 non-secure (U-Boot) | |||
| Security | DDRMCE | DDRMCE | ☑ | |||
3.2. Runtime assignment[edit | edit source]
3.2.1. On STM32MP13x lines [edit | edit source]
Click on to expand or collapse the legend...
| Domain | Peripheral | Runtime allocation | Comment
| ||
|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) | |||
| Security | DDRMCE | DDRMCE | ⬚ | ⬚ | |
4. Software frameworks and drivers[edit | edit source]
All system bus traffic going through an encrypted region is managed on-the-fly by the DDRMCE, automatically decrypting reads and encrypting writes: see the memory mapping.
5. How to assign and configure the peripheral[edit | edit source]
The DDRMCE configuration is generated via STM32CubeMX tool, according to the region characteristics (address, length, type). This configuration is applied during boot time by the FSBL (see Boot chain overview): TF-A.
6. References[edit | edit source]
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 