All the peripherals receive one or several clocks that are generated via RCC internal peripheral. RCC relies on several clocks sources (LSI, LSE, HSI, HSE, CSI) and four PLL in order to provide adequate input frequencies to all the peripherals. The clock tree covers all the system clock distribution aspects, from the clock sources to the consumer peripherals (internal and external), except clock gating management that is locally controlled by each peripheral driver.
1. Overview
The clock tree is managed via RCC internal peripheral hardware block and it is configured at different steps from the Cortex-A7:
- When the device is reset, all RCC registers take their reset values: the four PLL are disabled and most of the clock source selectors are pointing to the HSI.
- The ROM Code configures the minimum clock tree needed to boot on the selected boot device.
- TF-A BL2 has the same strategy as the ROM code, configuring the minimum clock tree needed for its execution, thanks to the configuration given in the device tree.
- OP-TEE completely configures the clock tree as expected, all the way up to Linux, thanks to the configuration given in the device tree.
- Linux may partly modify the clock tree at runtime thanks to SCMI clock services provided by OP-TEE secure OS. Information related to SCMI are taken from the device tree:
- Linux binding is available in Documentation/devicetree/bindings/clock/clock-bindings.txt (and surrounding files): 'fixed-clock' compatible, 'clocks' and 'assigned-clocks' properties are important concepts to understand the management of clocks providers/consumers.
Notice that STM32Cube (running on the Cortex-M4) does not control the clock tree setup so the configuration applied by the Cortex-A7 must provide suitable clocks to Cortex-M4, like it is explained in resource manager description. One exception to this rule is the engineering boot, allowing to directly load (and debug) the Cortex-M4 whereas the Cortex-A7 execution is stalled in the ROM code.
2. How to build a clock tree?
We encourage the use of STM32CubeMX to build the clock tree, and avoid having to know all internal peripherals details: the tool allows to select the peripherals that will be present on the board, fix the clock sources frequencies and automatically find an optimized clock tree. It is then able to generate the device tree that is directly consumed by the boot chain and the secure OS. Linux kernel will be able to modify the clock tree at run time thanks to SCMI clock services provided by OP-TEE. Building a clock tree is quite complex as it needs to take into account the constraints set by each internal and external peripheral, including external clock sources.
3. ST boards clock tree
This chapter ensures that all peripherals receive clocks with characteristics compatible with the specification (frequency, duty cycle, precision) on each ST board.
 Information
|
| See How to change the CPU frequency article for more information about the CPU frequency setting (PLL1P), including dynamic voltage and frequency scaling (DVFS) configuration. |
| Information
|
| The PLL4Q clock frequency is subject to dynamically change depending on the display video mode pixel clock configured by the LTDC Linux driver. See DRM KMS Overview - Set a particular video mode article for more information. |
3.1. STM32MP157x-EV1 Evaluation board 
case
This chapter shows the result of the boot time clock tree set by the FSBL TF-A, overlaid by the run time clock tree set by the Secure OS on STM32MP157x-EV1 Evaluation board .
Linux eventual runtime modifications are not covered here.
3.1.1. Clock tree
The following table shows what STM32MP157x-EV1 Evaluation board clock tree looks like, as a result of the boot chain execution with the device tree built with STM32CubeMX.
Component | Parent | Frequency | Used? | Comment |
-----------------------|---------|-----------------|--------|-----------------------------------|
LSI |N.A. | 0.032000 MHz | yes | Mandatory for IWDG, DAC
DAC |LSI | 0.032000 MHz | yes |
RNG1 |LSI | 0.032000 MHz | yes | Input frequency should be as low as possible
RNG2 |LSI | 0.032000 MHz | yes | Input frequency should be as low as possible
IWDG1 |LSI | 0.032000 MHz | yes |
IWDG2 |LSI | 0.032000 MHz | yes |
LSE |N.A. | 0.032768 MHz | yes |
RTC |LSE | 0.032768 MHz | yes |
TAMP |LSE | 0.032768 MHz | yes |
CEC |LSE | 0.032768 MHz | yes |
LPTIM4 |LSE | 0.032768 MHz | yes |
LPTIM5 |LSE | 0.032768 MHz | yes |
HSI |N.A. | 64.000000 MHz | yes |
SPI4 |HSI | 64.000000 MHz | no |
SPI5 |HSI | 64.000000 MHz | no |
SPI6 |HSI | 64.000000 MHz | yes |
I2C4 |HSI | 64.000000 MHz | yes | PMIC
I2C6 |HSI | 64.000000 MHz | no |
I2C1 |HSI | 64.000000 MHz | no |
I2C2 |HSI | 64.000000 MHz | yes | Rpi and peripherals
I2C3 |HSI | 64.000000 MHz | no |
I2C5 |HSI | 64.000000 MHz | yes | Rpi
USART1 |HSI | 64.000000 MHz | yes |
USART2 |HSI | 64.000000 MHz | no |
USART3 |HSI | 64.000000 MHz | yes | Rpi
UART4 |HSI | 64.000000 MHz | yes | Linux console
UART5 |HSI | 64.000000 MHz | no |
USART6 |HSI | 64.000000 MHz | no |
UART7 |HSI | 64.000000 MHz | no |
UART8 |HSI | 64.000000 MHz | no |
MCO1 |HSI | 64.000000 MHz | no | Available so can be used
HSE |N.A. | 24.000000 MHz | yes |
DSIPLL |HSE | 125.000000 MHz | no | DSI DPHY PLL
DSIBL |DSIPLL | 125.000000 MHz | no | DSI lanebyte clock
RTCDIV |HSE | 1.000000 MHz | yes | Only used when RTC source is HSE
ck_per |HSE | 24.000000 MHz | yes |
ADC |ck_per | 24.000000 MHz | yes | Can use internal divider to be < 40MHz
PLL1 |HSE | xxx MHz | yes |
PLL1P |PLL1 | xxx MHz | yes |
MPUDIV |PLL1P | xxx MHz | yes |
Cortex-A7 |PLL1P | xxx MHz | yes | 650 MHz or 800 MHz, see the information box above
MCO2 |Cortex-A7| xxx MHz | no | Available so can be used
PLL2 |HSE | 1066.000000 MHz | yes |
PLL2P |PLL2 | 266.500000 MHz | yes |
AXI |PLL2P | 266.500000 MHz | yes | < 266MHz
FMC |AXI | 266.500000 MHz | yes | NAND flash
QSPI |AXI | 266.500000 MHz | yes | NOR flash
SYSRAM |AXI | 266.500000 MHz | yes |
ROM |AXI | 266.500000 MHz | yes |
AHB5 |AXI | 266.500000 MHz | yes | < 266MHz
CRYP1 |AHB5 | 266.500000 MHz | yes |
HASH1 |AHB5 | 266.500000 MHz | yes |
GPIOZ |AHB5 | 266.500000 MHz | yes |
BKPSRAM |AHB5 | 266.500000 MHz | yes |
AHB6 |AXI | 266.500000 MHz | yes | < 266MHz
CRC1 |AHB6 | 266.500000 MHz | yes |
MDMA |AHB6 | 266.500000 MHz | yes |
USBH |AHB6 | 266.500000 MHz | yes | USB Host
APB4 |AHB6 | 133.250000 MHz | yes |
APB5 |AHB6 | 66.625000 MHz | yes |
BSEC |APB5 | 66.625000 MHz | yes | < 67MHz
ETZPC |APB5 | 66.625000 MHz | yes |
TZC |APB5 | 66.625000 MHz | yes |
DBGAPB |AXI | 133.250000 MHz | yes | JTAG & Coresight
DBGMCU |DBGAPB | 66.625000 MHz | yes |
STM |DBGAPB | 66.625000 MHz | yes |
PLL2Q |PLL2 | 533.000000 MHz | yes |
GPU |PLL2Q | 533.000000 MHz | yes | < 533MHz
PLL2R |PLL2 | 533.000000 MHz | yes |
DDR |PLL2R | 533.000000 MHz | yes | < 533MHz
PLL3 |HSE | 417.755859 MHz | yes |
PLL3P |PLL3 | 208.877930 MHz | yes |
MLAHB |PLL3P | 208.877930 MHz | yes | < 209MHz
Cortex-M4 |MLAHB | 208.877930 MHz | yes |
SRAM1 |MLAHB | 208.877930 MHz | yes |
SRAM2 |MLAHB | 208.877930 MHz | yes |
SRAM3 |MLAHB | 208.877930 MHz | yes |
RETRAM |MLAHB | 208.877930 MHz | yes |
AHB1 |MLAHB | 208.877930 MHz | yes | < 209MHz
AHB2 |MLAHB | 208.877930 MHz | yes | < 209MHz
DMA1 |AHB2 | 208.877930 MHz | yes |
DMA2 |AHB2 | 208.877930 MHz | yes |
DMAMUX |AHB2 | 208.877930 MHz | yes |
APB1 |MLAHB | 104.438965 MHz | yes |
LPTIM1 |APB1 | 104.438965 MHz | yes |
WWDG |APB1 | 104.438965 MHz | yes |
APB2 |MLAHB | 104.438965 MHz | yes |
TIM2 |MLAHB | 208.877930 MHz | yes | TIM Group 1
TIM3 |MLAHB | 208.877930 MHz | yes | TIM Group 1
TIM4 |MLAHB | 208.877930 MHz | yes | TIM Group 1
TIM5 |MLAHB | 208.877930 MHz | yes | TIM Group 1
TIM6 |MLAHB | 208.877930 MHz | yes | TIM Group 1
TIM7 |MLAHB | 208.877930 MHz | yes | TIM Group 1
TIM12 |MLAHB | 208.877930 MHz | yes | TIM Group 1
TIM13 |MLAHB | 208.877930 MHz | yes | TIM Group 1
TIM14 |MLAHB | 208.877930 MHz | yes | TIM Group 1
TIM1 |MLAHB | 208.877930 MHz | yes | TIM Group 2
TIM8 |MLAHB | 208.877930 MHz | yes | TIM Group 2
TIM15 |MLAHB | 208.877930 MHz | yes | TIM Group 2
TIM16 |MLAHB | 208.877930 MHz | yes | TIM Group 2
TIM17 |MLAHB | 208.877930 MHz | yes | TIM Group 2
APB3 |MLAHB | 104.438965 MHz | yes |
LPTIM2 |APB3 | 104.438965 MHz | yes |
LPTIM3 |APB3 | 104.438965 MHz | yes |
SYSCFG |APB3 | 104.438965 MHz | yes |
VREFBUF |APB3 | 104.438965 MHz | yes |
DTS |APB3 | 104.438965 MHz | yes |
HDP |APB3 | 104.438965 MHz | yes |
AHB3 |MLAHB | 208.877930 MHz | yes | < 209MHz
CRC2 |AHB3 | 208.877930 MHz | yes |
CRYP2 |AHB3 | 208.877930 MHz | yes |
HASH2 |AHB3 | 208.877930 MHz | yes |
DCMI |AHB3 | 208.877930 MHz | yes | Camera
IPCC |AHB3 | 208.877930 MHz | yes | Mailbox
AHB4 |MLAHB | 208.877930 MHz | yes | < 209MHz
PWR |AHB4 | 208.877930 MHz | yes |
RCC |AHB4 | 208.877930 MHz | yes |
GPIOA-K |AHB4 | 208.877930 MHz | yes |
EXTI |AHB4 | 208.877930 MHz | yes |
PLL3Q |PLL3 | 24.573874 MHz | yes |
SPI1 |PLL3Q | 24.573874 MHz | no |
SPI2 |PLL3Q | 24.573874 MHz | no |
SPI3 |PLL3Q | 24.573874 MHz | no |
DFSDM |PLL3Q | 24.573874 MHz | yes | Digital micro
SAI1 |PLL3Q | 24.573874 MHz | no |
SAI2 |PLL3Q | 24.573874 MHz | yes | AudCodec 48kHz (use PLL3R for 44.1kHz)
SAI3 |PLL3Q | 24.573874 MHz | no |
SAI4 |PLL3Q | 24.573874 MHz | yes | SPDIF TX 48kHz (use PLL3R for 44.1kHz)
PLL3R |PLL3 | 11.290699 MHz | yes |
PLL4 |HSE | 594.000000 MHz | yes |
PLL4P |PLL4 | 99.000000 MHz | yes |
ETH |PLL4P | 99.000000 MHz | yes | PTP ref clock (ETH clocked by RGMII PHY)
SDMMC1 |PLL4P | 99.000000 MHz | yes | µSD card
SDMMC2 |PLL4P | 99.000000 MHz | yes | eMMC
SDMMC3 |PLL4P | 99.000000 MHz | yes |
SPDIF |PLL4P | 99.000000 MHz | yes | SPDIF RX
PLL4Q |PLL4 | 74.250000 MHz | yes |
LCD |PLL4Q | 74.250000 MHz | yes | LTDC & DSI display pixel clock
PLL4R |PLL4 | 74.250000 MHz | yes |
FDCAN |PLL4R | 74.250000 MHz | yes | Should be as high as possible and < 100MHz
STGEN |HSE | 24.000000 MHz | yes |
USBPHYC |HSE | 24.000000 MHz | yes | USB PHY Ctrl for USB Host and OTG
USBPLL |USBPHYC | 48.000000 MHz | yes |
USBO |USBPLL | 48.000000 MHz | yes | USB OTG
CSI |N.A. | 4.000000 MHz | yes | Mandatory for IO compensation
-----------------------|---------|-----------------|--------|-----------------------------------|
As mentioned in previous chapters, RCC configuration is done in two steps, first by the first stage boot loader (FSBL TF-A) and then by the secure OS (OP-TEE).
3.1.2. Device tree
Here are the corresponding device tree rcc sub node properties in fdts/stm32mp157c-ed1.dts consumed by the first stage boot loader (FSBL TF-A) to configure the clock tree above:
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
CLK_ETH_PLL4P
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_PLL3Q
CLK_SPI2S23_PLL3Q
CLK_SPI45_HSI
CLK_SPI6_HSI
CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSE
CLK_I2C12_HSI
CLK_I2C35_HSI
CLK_UART1_HSI
CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
CLK_RNG1_CSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
st,clkdiv = <
DIV(DIV_MPU, 1)
DIV(DIV_AXI, 0)
DIV(DIV_MCU, 0)
DIV(DIV_APB1, 1)
DIV(DIV_APB2, 1)
DIV(DIV_APB3, 1)
DIV(DIV_APB4, 1)
DIV(DIV_APB5, 2)
DIV(DIV_RTC, 23)
DIV(DIV_MCO1, 0)
DIV(DIV_MCO2, 0)
>;
st,pll_vco {
pll2_vco_1066Mhz: pll2-vco-1066Mhz {
src = <CLK_PLL12_HSE>;
divmn = <2 65>;
frac = <0x1400>;
};
pll3_vco_417Mhz: pll3-vco-417Mhz {
src = <CLK_PLL3_HSE>;
divmn = <1 33>;
frac = <0x1a04>;
};
pll4_vco_594Mhz: pll4-vco-594Mhz {
src = <CLK_PLL4_HSE>;
divmn = <3 98>;
};
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
reg = <1>;
st,pll = <&pll2_cfg1>;
pll2_cfg1: pll2_cfg1 {
st,pll_vco = <&pll2_vco_1066Mhz>;
st,pll_div_pqr = <1 0 0>;
};
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
compatible = "st,stm32mp1-pll";
reg = <2>;
st,pll = <&pll3_cfg1>;
pll3_cfg1: pll3_cfg1 {
st,pll_vco = <&pll3_vco_417Mhz>;
st,pll_div_pqr = <1 16 36>;
};
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
st,pll = <&pll4_cfg1>;
pll4_cfg1: pll4_cfg1 {
st,pll_vco = <&pll4_vco_594Mhz>;
st,pll_div_pqr = <5 7 7>;
};
};
Here are the corresponding device tree rcc sub node properties in core/arch/arm/dts/stm32mp157c-ed1.dts consumed by the secure OS (OP-TEE) to configure the clock tree above:
&rcc {
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
CLK_ETH_PLL4P
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_PLL3Q
CLK_SPI2S23_PLL3Q
CLK_SPI45_HSI
CLK_SPI6_HSI
CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSE
CLK_I2C12_HSI
CLK_I2C35_HSI
CLK_UART1_HSI
CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
CLK_RNG1_CSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
st,clkdiv = <
DIV(DIV_MPU, 1)
DIV(DIV_AXI, 0)
DIV(DIV_MCU, 0)
DIV(DIV_APB1, 1)
DIV(DIV_APB2, 1)
DIV(DIV_APB3, 1)
DIV(DIV_APB4, 1)
DIV(DIV_APB5, 2)
DIV(DIV_RTC, 23)
DIV(DIV_MCO1, 0)
DIV(DIV_MCO2, 0)
>;
st,pll_vco {
pll2_vco_1066Mhz: pll2-vco-1066Mhz {
src = <CLK_PLL12_HSE>;
divmn = <2 65>;
frac = <0x1400>;
};
pll3_vco_417Mhz: pll3-vco-417Mhz {
src = <CLK_PLL3_HSE>;
divmn = <1 33>;
frac = <0x1a04>;
};
pll4_vco_594Mhz: pll4-vco-594Mhz {
src = <CLK_PLL4_HSE>;
divmn = <3 98>;
};
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
reg = <1>;
st,pll = <&pll2_cfg1>;
pll2_cfg1: pll2_cfg1 {
st,pll_vco = <&pll2_vco_1066Mhz>;
st,pll_div_pqr = <1 0 0>;
};
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
compatible = "st,stm32mp1-pll";
reg = <2>;
st,pll = <&pll3_cfg1>;
pll3_cfg1: pll3_cfg1 {
st,pll_vco = <&pll3_vco_417Mhz>;
st,pll_div_pqr = <1 16 36>;
};
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
st,pll = <&pll4_cfg1>;
pll4_cfg1: pll4_cfg1 {
st,pll_vco = <&pll4_vco_594Mhz>;
st,pll_div_pqr = <5 7 7>;
};
};
};
Here the only difference is the RTC source clock selection, done only one time in OP-TEE for cold boot and the rest of clock tree stay unchanged.
3.2. STM32MP157x-DK2 Discovery kit case
This chapter shows the result of the boot time clock tree set by the FSBL TF-A, overlaid by the run time clock tree set by the Secure OS on STM32MP157x-DK2 Discovery kit .
Linux eventual runtime modifications are not covered here.
3.2.1. Clock tree
The following table shows whatSTM32MP157x-DK2 Discovery kit clock tree looks like, as a result of the boot chain execution with the device tree built with STM32CubeMX.
Component | Parent | Frequency | Used? | Comment |
-----------------------|---------|-----------------|--------|-----------------------------------|
LSI |N.A. | 0.032000 MHz | yes | Mandatory for IWDG, DAC
DAC |LSI | 0.032000 MHz | no |
RNG1 |LSI | 0.032000 MHz | yes | Input frequency should be as low as possible
RNG2 |LSI | 0.032000 MHz | yes | Input frequency should be as low as possible
IWDG1 |LSI | 0.032000 MHz | yes |
IWDG2 |LSI | 0.032000 MHz | yes |
LSE |N.A. | 0.032768 MHz | yes | Mandatory for DTS
RTC |LSE | 0.032768 MHz | yes |
TAMP |LSE | 0.032768 MHz | yes |
CEC |LSE | 0.032768 MHz | yes |
LPTIM4 |LSE | 0.032768 MHz | yes |
LPTIM5 |LSE | 0.032768 MHz | yes |
HSI |N.A. | 64.000000 MHz | yes |
SPI4 |HSI | 64.000000 MHz | yes | Arduino
SPI5 |HSI | 64.000000 MHz | yes | Rpi
SPI6 |HSI | 64.000000 MHz | no |
I2C4 |HSI | 64.000000 MHz | yes | PMIC
I2C6 |HSI | 64.000000 MHz | no |
I2C1 |HSI | 64.000000 MHz | yes | Rpi and peripherals
I2C2 |HSI | 64.000000 MHz | no |
I2C3 |HSI | 64.000000 MHz | no |
I2C5 |HSI | 64.000000 MHz | yes | Rpi and Arduino
USART1 |HSI | 64.000000 MHz | no |
USART2 |HSI | 64.000000 MHz | yes | Bluetooth
USART3 |HSI | 64.000000 MHz | yes | Rpi
UART4 |HSI | 64.000000 MHz | yes | Linux console
UART5 |HSI | 64.000000 MHz | no |
USART6 |HSI | 64.000000 MHz | no |
UART7 |HSI | 64.000000 MHz | yes | Arduino
UART8 |HSI | 64.000000 MHz | no |
MCO1 |HSI | 64.000000 MHz | no | Available so can be used
HSE |N.A. | 24.000000 MHz | yes |
DSIPLL |HSE | 125.000000 MHz | no | DSI DPHY PLL
DSIBL |DSIPLL | 125.000000 MHz | no | DSI lanebyte clock
RTCDIV |HSE | 1.000000 MHz | yes | Only used when RTC source is HSE
ck_per |HSE | 24.000000 MHz | yes |
ADC |ck_per | 24.000000 MHz | yes | Can use internal divider to be < 40MHz
PLL1 |HSE | xxx MHz | yes |
PLL1P |PLL1 | xxx MHz | yes |
MPUDIV |PLL1P | xxx MHz | yes |
Cortex-A7 |PLL1P | xxx MHz | yes | 650 MHz or 800 MHz, see the information box above
MCO2 |Cortex-A7| xxx MHz | no | Available so can be used
PLL2 |HSE | 1066.000000 MHz | yes |
PLL2P |PLL2 | 266.500000 MHz | yes |
AXI |PLL2P | 266.500000 MHz | yes | < 266MHz
FMC |AXI | 266.500000 MHz | no |
QSPI |AXI | 266.500000 MHz | no |
SYSRAM |AXI | 266.500000 MHz | yes |
ROM |AXI | 266.500000 MHz | yes |
AHB5 |AXI | 266.500000 MHz | yes | < 266MHz
CRYP1 |AHB5 | 266.500000 MHz | yes |
HASH1 |AHB5 | 266.500000 MHz | yes |
GPIOZ |AHB5 | 266.500000 MHz | yes |
BKPSRAM |AHB5 | 266.500000 MHz | yes |
AHB6 |AXI | 266.500000 MHz | yes | < 266MHz
CRC1 |AHB6 | 266.500000 MHz | yes |
MDMA |AHB6 | 266.500000 MHz | yes |
USBH |AHB6 | 266.500000 MHz | yes | USB Host
APB4 |AHB6 | 133.250000 MHz | yes |
APB5 |AHB6 | 66.625000 MHz | yes |
BSEC |APB5 | 66.625000 MHz | yes | < 67MHz
ETZPC |APB5 | 66.625000 MHz | yes |
TZC |APB5 | 66.625000 MHz | yes |
DBGAPB |AXI | 133.250000 MHz | yes | JTAG & Coresight
DBGMCU |DBGAPB | 66.625000 MHz | yes |
STM |DBGAPB | 66.625000 MHz | no |
PLL2Q |PLL2 | 533.000000 MHz | yes |
GPU |PLL2Q | 533.000000 MHz | yes | < 533MHz
PLL2R |PLL2 | 533.000000 MHz | yes |
DDR |PLL2R | 533.000000 MHz | yes | < 533MHz
PLL3 |HSE | 417.755859 MHz | yes |
PLL3P |PLL3 | 208.877930 MHz | yes |
MLAHB |PLL3P | 208.877930 MHz | yes | < 209MHz
Cortex-M4 |MLAHB | 208.877930 MHz | yes |
SRAM1 |MLAHB | 208.877930 MHz | yes |
SRAM2 |MLAHB | 208.877930 MHz | yes |
SRAM3 |MLAHB | 208.877930 MHz | yes |
RETRAM |MLAHB | 208.877930 MHz | yes |
AHB1 |MLAHB | 208.877930 MHz | yes | < 209MHz
AHB2 |MLAHB | 208.877930 MHz | yes | < 209MHz
DMA1 |AHB2 | 208.877930 MHz | yes |
DMA2 |AHB2 | 208.877930 MHz | yes |
DMAMUX |AHB2 | 208.877930 MHz | yes |
APB1 |MLAHB | 104.438965 MHz | yes |
LPTIM1 |APB1 | 104.438965 MHz | yes |
WWDG |APB1 | 104.438965 MHz | yes |
APB2 |MLAHB | 104.438965 MHz | yes |
TIM2 |MLAHB | 208.877930 MHz | yes | TIM Group 1
TIM3 |MLAHB | 208.877930 MHz | yes | TIM Group 1
TIM4 |MLAHB | 208.877930 MHz | yes | TIM Group 1
TIM5 |MLAHB | 208.877930 MHz | yes | TIM Group 1
TIM6 |MLAHB | 208.877930 MHz | yes | TIM Group 1
TIM7 |MLAHB | 208.877930 MHz | yes | TIM Group 1
TIM12 |MLAHB | 208.877930 MHz | yes | TIM Group 1
TIM13 |MLAHB | 208.877930 MHz | yes | TIM Group 1
TIM14 |MLAHB | 208.877930 MHz | yes | TIM Group 1
TIM1 |MLAHB | 208.877930 MHz | yes | TIM Group 2
TIM8 |MLAHB | 208.877930 MHz | yes | TIM Group 2
TIM15 |MLAHB | 208.877930 MHz | yes | TIM Group 2
TIM16 |MLAHB | 208.877930 MHz | yes | TIM Group 2
TIM17 |MLAHB | 208.877930 MHz | yes | TIM Group 2
APB3 |MLAHB | 104.438965 MHz | yes |
LPTIM2 |APB3 | 104.438965 MHz | yes |
LPTIM3 |APB3 | 104.438965 MHz | yes |
SYSCFG |APB3 | 104.438965 MHz | yes |
VREFBUF |APB3 | 104.438965 MHz | yes |
DTS |APB3 | 104.438965 MHz | yes |
HDP |APB3 | 104.438965 MHz | no |
AHB3 |MLAHB | 208.877930 MHz | yes | < 209MHz
CRC2 |AHB3 | 208.877930 MHz | yes |
CRYP2 |AHB3 | 208.877930 MHz | yes |
HASH2 |AHB3 | 208.877930 MHz | yes |
DCMI |AHB3 | 208.877930 MHz | no |
IPCC |AHB3 | 208.877930 MHz | yes | Mailbox
AHB4 |MLAHB | 208.877930 MHz | yes | < 209MHz
PWR |AHB4 | 208.877930 MHz | yes |
RCC |AHB4 | 208.877930 MHz | yes |
GPIOA-K |AHB4 | 208.877930 MHz | yes |
EXTI |AHB4 | 208.877930 MHz | yes |
PLL3Q |PLL3 | 24.573874 MHz | yes |
SPI1 |PLL3Q | 24.573874 MHz | yes | SPI2S1 for BT PCM
SPI2 |PLL3Q | 24.573874 MHz | yes | SPI2S2 for HDMI
SPI3 |PLL3Q | 24.573874 MHz | no |
DFSDM |PLL3Q | 24.573874 MHz | no |
SAI1 |PLL3Q | 24.573874 MHz | no |
SAI2 |PLL3Q | 24.573874 MHz | yes | AudCodec 48kHz (use PLL3R for 44.1kHz)
SAI3 |PLL3Q | 24.573874 MHz | no |
SAI4 |PLL3Q | 24.573874 MHz | no |
PLL3R |PLL3 | 11.290699 MHz | yes |
PLL4 |HSE | 594.000000 MHz | yes |
PLL4P |PLL4 | 99.000000 MHz | yes |
ETH |PLL4P | 99.000000 MHz | yes | PTP ref clock (ETH clocked by RGMII PHY)
SDMMC1 |PLL4P | 99.000000 MHz | yes | µSD card
SDMMC2 |PLL4P | 99.000000 MHz | yes | Wifi
SDMMC3 |PLL4P | 99.000000 MHz | yes | Rpi
SPDIF |PLL4P | 99.000000 MHz | no |
PLL4Q |PLL4 | 74.250000 MHz | yes |
LCD |PLL4Q | 74.250000 MHz | yes | LTDC & DSI display pixel clock
PLL4R |PLL4 | 74.250000 MHz | yes |
FDCAN |PLL4R | 74.250000 MHz | no |
STGEN |HSE | 24.000000 MHz | yes |
USBPHYC |HSE | 24.000000 MHz | yes | USB PHY Ctrl for USB Host and OTG
USBPLL |USBPHYC | 48.000000 MHz | yes |
USBO |USBPLL | 48.000000 MHz | yes | USB OTG
CSI |N.A. | 4.000000 MHz | yes | Mandatory for IO compensation
-----------------------|---------|-----------------|--------|-----------------------------------|
3.2.2. Device tree
As mentioned in previous chapters, RCC configuration is done in two steps, first by the first stage boot loader (FSBL TF-A) and then by the secure OS (OP-TEE).
Here are the corresponding device tree rcc sub node properties in fdts/stm32mp15xx-dkx.dtsi consumed by the first stage boot loader (FSBL TF-A) to configure the clock tree above:
&rcc {
compatible = "st,stm32mp1-rcc-secure", "st,stm32mp1-rcc", "syscon";
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
CLK_ETH_PLL4P
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_PLL3Q
CLK_SPI2S23_PLL3Q
CLK_SPI45_HSI
CLK_SPI6_HSI
CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSE
CLK_I2C12_HSI
CLK_I2C35_HSI
CLK_UART1_HSI
CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
CLK_RNG1_CSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
st,clkdiv = <
DIV(DIV_MPU, 1)
DIV(DIV_AXI, 0)
DIV(DIV_MCU, 0)
DIV(DIV_APB1, 1)
DIV(DIV_APB2, 1)
DIV(DIV_APB3, 1)
DIV(DIV_APB4, 1)
DIV(DIV_APB5, 2)
DIV(DIV_RTC, 23)
DIV(DIV_MCO1, 0)
DIV(DIV_MCO2, 0)
>;
st,pll_vco {
pll2_vco_1066Mhz: pll2-vco-1066Mhz {
src = <CLK_PLL12_HSE>;
divmn = <2 65>;
frac = <0x1400>;
};
pll3_vco_417Mhz: pll3-vco-417Mhz {
src = <CLK_PLL3_HSE>;
divmn = <1 33>;
frac = <0x1a04>;
};
pll4_vco_594Mhz: pll4-vco-594Mhz {
src = <CLK_PLL4_HSE>;
divmn = <3 98>;
};
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
reg = <1>;
st,pll = <&pll2_cfg1>;
pll2_cfg1: pll2_cfg1 {
st,pll_vco = <&pll2_vco_1066Mhz>;
st,pll_div_pqr = <1 0 0>;
};
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
compatible = "st,stm32mp1-pll";
reg = <2>;
st,pll = <&pll3_cfg1>;
pll3_cfg1: pll3_cfg1 {
st,pll_vco = <&pll3_vco_417Mhz>;
st,pll_div_pqr = <1 16 36>;
};
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
st,pll = <&pll4_cfg1>;
pll4_cfg1: pll4_cfg1 {
st,pll_vco = <&pll4_vco_594Mhz>;
st,pll_div_pqr = <5 7 7>;
};
};
};
Here are the corresponding device tree rcc sub node properties in core/arch/arm/dts/stm32mp15xx-dkx.dtsi consumed by the secure OS (OP-TEE) to configure the clock tree above:
&rcc {
compatible = "st,stm32mp1-rcc-secure", "st,stm32mp1-rcc", "syscon";
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
CLK_CKPER_HSE
CLK_FMC_ACLK
CLK_QSPI_ACLK
CLK_ETH_PLL4P
CLK_SDMMC12_PLL4P
CLK_DSI_DSIPLL
CLK_STGEN_HSE
CLK_USBPHY_HSE
CLK_SPI2S1_PLL3Q
CLK_SPI2S23_PLL3Q
CLK_SPI45_HSI
CLK_SPI6_HSI
CLK_I2C46_HSI
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSE
CLK_I2C12_HSI
CLK_I2C35_HSI
CLK_UART1_HSI
CLK_UART24_HSI
CLK_UART35_HSI
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
CLK_SAI4_PLL3Q
CLK_RNG1_CSI
CLK_RNG2_LSI
CLK_LPTIM1_PCLK1
CLK_LPTIM23_PCLK3
CLK_LPTIM45_LSE
>;
st,clkdiv = <
DIV(DIV_MPU, 1)
DIV(DIV_AXI, 0)
DIV(DIV_MCU, 0)
DIV(DIV_APB1, 1)
DIV(DIV_APB2, 1)
DIV(DIV_APB3, 1)
DIV(DIV_APB4, 1)
DIV(DIV_APB5, 2)
DIV(DIV_RTC, 23)
DIV(DIV_MCO1, 0)
DIV(DIV_MCO2, 0)
>;
st,pll_vco {
pll2_vco_1066Mhz: pll2-vco-1066Mhz {
src = <CLK_PLL12_HSE>;
divmn = <2 65>;
frac = <0x1400>;
};
pll3_vco_417Mhz: pll3-vco-417Mhz {
src = <CLK_PLL3_HSE>;
divmn = <1 33>;
frac = <0x1a04>;
};
pll4_vco_594Mhz: pll4-vco-594Mhz {
src = <CLK_PLL4_HSE>;
divmn = <3 98>;
};
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
reg = <1>;
st,pll = <&pll2_cfg1>;
pll2_cfg1: pll2_cfg1 {
st,pll_vco = <&pll2_vco_1066Mhz>;
st,pll_div_pqr = <1 0 0>;
};
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
compatible = "st,stm32mp1-pll";
reg = <2>;
st,pll = <&pll3_cfg1>;
pll3_cfg1: pll3_cfg1 {
st,pll_vco = <&pll3_vco_417Mhz>;
st,pll_div_pqr = <1 16 36>;
};
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;
st,pll = <&pll4_cfg1>;
pll4_cfg1: pll4_cfg1 {
st,pll_vco = <&pll4_vco_594Mhz>;
st,pll_div_pqr = <5 7 7>;
};
};
};
Here the only difference is the RTC source clock selection, done only one time in OP-TEE for cold boot and the rest of clock tree is unchanged.