STM32MP25 peripherals overview: Difference between revisions

Revision as of 18:02, 11 December 2023↑

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This article lists all internal peripherals embedded in STM32MP25x lines and shows the assignment possibilities to the execution contexts for each one of them.
From this article, you can also access to individual peripheral articles with information related to the overview and configuration aspects.

1. Internal peripherals overview[edit | edit source]↑

The figure below shows all peripherals embedded in STM32MP25x lines , grouped per functional domains that are reused in many places of this wiki to structure the articles.
Several execution contexts exist on STM32MP25x lines ^[1], corresponding to the different Arm cores and associated security modes:

Arm dual core Cortex-A35 secure (Trustzone), running ROM code and TF-A BL2 at boot time, and running OP-TEE and/or TF-A BL31 at runtime
Arm dual core Cortex-A35 non secure , running U-Boot at boot time, and running Linux at runtime
Arm Cortex-M33 secure (Trustzone), running TF-M
Arm Cortex-M33 non-secure , running STM32Cube

The legend below shows how assigned and shared peripherals are identified in the assignment diagram that follows:

When a peripheral box owns execution context color, that means the assignment of this peripheral is fixed by hardware to the execution context.
When a peripheral box owns a mix of two execution colors that means this peripheral is shared by hardware between the two execution contexts.
When a peripheral box has dark gray color, that means this peripheral is protected by RIF and could be assigned to any execution context.
When a peripheral box has light gray color, that means this peripheral is a RIF-aware peripheral. This peripheral owns several features which can be assigned independently to any execution context.

Internal peripheral assignment tables list assignment capabilities for each peripheral.

Both the diagram below and the following summary tables (in Internal peripherals runtime assignment and Internal peripherals boot time assignment chapters below) are clickable in order to jump to each peripheral overview articles and get more detailed information (like software frameworks used to control them). They list STMicroelectronics recommendations. The STM32MP25 reference manual ^[2] may expose more possibilities than what is shown here.

STM32MP25 internal peripherals overview

2. Internal peripherals runtime assignment[edit | edit source]↑

Click on to expand or collapse the legend...

ADF internal peripheral ETHSW internal peripheral

Domain	Peripheral	Runtime allocation						Comment
Domain	Peripheral	Instance	Cortex-A35 secure (OP-TEE / TF-A BL31)	Cortex-A35 non-secure (Linux)	Cortex-M33 secure (TF-M)	Cortex-M33 non-secure (STM32Cube)	Cortex-M0+ (STM32Cube)	Comment
Core/Processors	Arm^® Cortex^®-A35	Arm^® Cortex^®-A35	✓^OP-TEE ✓^{TF-A BL31}	✓
Core/Processors	Arm^® Cortex^®-M33 (coprocessor)	Arm^® Cortex^®-M33 (coprocessor)	☐^OP-TEE	☐	☐	✓		Controlled by LInux or OP-TEE. Running the STM32CubeMP2 firmware.
Core/Processors	Arm^® Cortex^®-M0+ (coprocessor)	Arm^® Cortex^®-M0+ (coprocessor)	☐^OP-TEE	☐	☐	☐
Analog	VREFBUF	VREFBUF	☑^OP-TEE	☐	☐	☐		OP-TEE offers SCMI regulator service to manage VREFBUF
Analog	ADC	ADC12	☐^OP-TEE	☐	⬚	☐
Analog	ADC	ADC3	☐^OP-TEE	☐	⬚	☑		ADC3 may be used by the UCSI firmware to measure the Vbus level on the Type-C connector.
Analog	MDF	MDF1	⬚^OP-TEE	☐	⬚	☐
Low speed interface or audio	SPI	SPI2S1	⬚^OP-TEE	☐	⬚	☐
		SPI2S2	⬚^OP-TEE	☐	⬚	☐
		SPI2S3	⬚^OP-TEE	☐	⬚	☐
		SPI4	⬚^OP-TEE	☐	⬚	☐
		SPI5	⬚^OP-TEE	☐	⬚	☐
		SPI6	⬚^OP-TEE	☐	⬚	☐
		SPI7	⬚^OP-TEE	☐	⬚	☐
		SPI8	⬚^OP-TEE	☐	⬚	☐	☐
Audio	SPDIFRX	SPDIFRX	⬚^OP-TEE	☐	⬚	☐
Audio	SAI	SAI1	⬚^OP-TEE	☐	⬚	☐
		SAI2	⬚^OP-TEE	☐	⬚	☐
		SAI3	⬚^OP-TEE	☐	⬚	☐
		SAI4	⬚^OP-TEE	☐	⬚	☐
Coprocessor	IPCC	IPCC1	☐^OP-TEE	☐	☐	☐		Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Coprocessor	IPCC	IPCC2	☐^OP-TEE	☐	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core	SYSCFG	SYSCFG	☑	☑	☑	☑
Core	STGEN	STGEN	☑^OP-TEE ☑^{TF-A BL31}	Read-only ^(STGENR)	Read-only ^(STGENR)	Read-only ^(STGENR)
Core	RTC	RTC	☐^OP-TEE	☐	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core/DMA	HPDMA	HPDMAx (x = 1 to 3)	☐^OP-TEE	☐	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core/DMA	LPDMA	LPDMA	☐^OP-TEE	☐	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core/Interrupts	EXTI	EXTI1	☐^OP-TEE	☐	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core/Interrupts	EXTI	EXTI2	☐^OP-TEE	☐	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core/Interrupts	GIC	GIC	✓^OP-TEE ✓^{TF-A BL31}	✓
Core/IOs	GPIO	GPIOA-K	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐		Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core/IOs	GPIO	GPIOZ	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Core/RAM	SYSRAM	SYSRAM	☑^BL31 ☐^OP-TEE	☑	☐	☐		Cortex-A35 secure section required for low power entry and exit
Core/RAM	DDRCTRL	DDR	☑^{TF-A BL31}	⬚	☐	⬚
Core/RAM	BKPSRAM	BKPSRAM	⬚^OP-TEE ☑^{TF-A BL31}	⬚	☑	⬚		TF-M uses BKPSRAM for ITS (Internal Trusted Storage)
Core/RAM	RETRAM	RETRAM	☐^OP-TEE ☐^{TF-A BL31}	⬚	☑	☐
Core/RAM	SRAM	SRAM1	☑^OP-TEE ☐^BL31	☐	☐	☐		OP-TEE populate OTP shadow region
Core/RAM	SRAM	SRAM2	☐^OP-TEE ☐^BL31	☐	☐	☐
Core/RAM	LPSRAM	LPSRAM1	☐^OP-TEE ☐^BL31	☐	☐	☐	☑	Should contains Cortex-M0+ firmware code
		LPSRAM2	☐^OP-TEE ☐^BL31	☐	☐	☐	☑	Should contains Cortex-M0+ firmware data
		LPSRAM3	☐^OP-TEE ☐^BL31	☐	☐	☐	☑
Core/Timers	TIM	TIM1	☐^OP-TEE	☐	⬚	☐
		TIM10	☐^OP-TEE	☐	⬚	☐
		TIM11	☐^OP-TEE	☐	⬚	☐
		TIM12	☐^OP-TEE	☐	⬚	☐
		TIM13	☐^OP-TEE	☐	⬚	☐
		TIM14	☐^OP-TEE	☐	⬚	☐
		TIM15	☐^OP-TEE	☐	⬚	☐
		TIM16	☐^OP-TEE	☐	⬚	☐
		TIM17	☐^OP-TEE	☐	⬚	☐
		TIM2	☐^OP-TEE	☐	⬚	☐
		TIM20	☐^OP-TEE	☐	⬚	☐
		TIM3	☐^OP-TEE	☐	⬚	☐
		TIM4	☐^OP-TEE	☐	⬚	☐
		TIM5	☐^OP-TEE	☐	⬚	☐
		TIM6	☐^OP-TEE	☐	⬚	☐
		TIM7	☐^OP-TEE	☐	⬚	☐
		TIM8	☐^OP-TEE	☐	⬚	☐
Core/Timers	LPTIM	LPTIM1	☐^OP-TEE	☐	⬚	☐		LPTIM1 can be used for HSE monitoring.
		LPTIM2	☐^OP-TEE	☐	⬚	☐
		LPTIM3	☐^OP-TEE	☐	⬚	☐	☐
		LPTIM4	☐^OP-TEE	☐	⬚	☐	☐
		LPTIM5	☐^OP-TEE	☐	⬚	☐	☐
Core/Watchdog	IWDG	IWDG1	☑^OP-TEE ☑^{TF-A BL31}	☐
		IWDG2	☐^OP-TEE ☐^{TF-A BL31}	☑
		IWDG3			☑	☐
		IWDG4			☐	☑
		IWDG5					☑
Core/Watchdog	WWDG	WWDG1			⬚	☐
Core/Watchdog	WWDG	WWDG2					☐
High speed interface	USB3DR	USB3DR	⬚^OP-TEE	☐	⬚	⬚
High speed interface	USBH	USBH	⬚^OP-TEE	☐	⬚	⬚
High speed interface	UCPD	UCPD1	⬚^OP-TEE	⬚	⬚	☐
High speed interface	COMBOPHY	COMBOPHY	⬚^OP-TEE	☐	⬚	⬚
High speed interface	USB2PHY	USB2PHY1	⬚^OP-TEE ⬚^{TF-A BL31}	☐	⬚	☐		Not a RIF aware, used as per allocation of USBH
High speed interface	USB2PHY	USB2PHY2	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐		Not a RIF aware, used as per allocation of USB3DR
High speed interface	PCIe	PCIe	⬚^OP-TEE	☐				The PCIe and the USB3DR running at USB3 speed are mutually exclusive. Both require to use the ComboPHY.
Low speed interface	USART	UART4	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		UART5	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		UART7	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		UART8	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		UART9	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		USART1	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		USART2	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		USART3	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
		USART6	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐
Low speed interface	I2C	I2C1	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐
		I2C2	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐
		I2C3	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐
		I2C4	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐
		I2C5	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐
		I2C6	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐
		I2C7	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐
		I2C8	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐	☐
Low speed interface	I3C	I3C1	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐
		I3C2	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐
		I3C3	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐
		I3C4	☐^OP-TEE ⬚^{TF-A BL31}	☐	☐	☐	☐
Mass storage	OCTOSPI	OCTOSPI1	⬚^OP-TEE	☐	☐	☐		OP-TEE need to access OCTOSPI1 at boot time to set OSPIM mode
Mass storage	OCTOSPI	OCTOSPI2	⬚^OP-TEE	☐	☐	☐		OP-TEE need to access OCTOSPI2 at boot time to set OSPIM mode
Mass storage	OCTOSPIM	OCTOSPIM	☐^OP-TEE	☐	☐	☐
Mass storage	FMC	FMC	☐^OP-TEE	☐	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Mass storage	SDMMC	SDMMC1	⬚^OP-TEE	☐	⬚	☐
		SDMMC2	⬚^OP-TEE	☐	⬚	☐
		SDMMC3	⬚^OP-TEE	☐	⬚	☐
Networking	FDCAN	FDCAN1	⬚^OP-TEE	☐	⬚	☐
		FDCAN2	⬚^OP-TEE	☐	⬚	☐
		FDCAN3	⬚^OP-TEE	☐	⬚	☐
Power & Thermal	RCC	RCC	✓^OP-TEE ✓^{TF-A BL31}	✓	✓	✓	✓	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Power & Thermal	PWR	PWR	☐^OP-TEE ☐^{TF-A BL31}	☐	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Power & Thermal	DTS	DTS	⬚^OP-TEE	☐		⬚
Security	BSEC	BSEC	✓^OP-TEE ✓^{TF-A BL31}
Security	HASH	HASH	☐^OP-TEE	☐	☐	☐
Security	CRYP	CRYP1	☐^OP-TEE	☐	☐	☐
Security	CRYP	CRYP2	☐^OP-TEE	☐	☐	☐
Security	CRC	CRC	⬚^OP-TEE	☐	⬚	☐
Security	SAES	SAES	☐^OP-TEE	⬚	☐	⬚
Security	TAMP	TAMP	✓^OP-TEE	⬚	⬚	⬚		Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Security	OTFDEC	OTFDEC1	⬚^OP-TEE	⬚	⬚	⬚
Security	OTFDEC	OTFDEC2	⬚^OP-TEE	⬚	⬚	⬚
Security	PKA	PKA	☐^OP-TEE	⬚	☐	⬚
Security	RIFSC	RIFSC	☑^OP-TEE	⬚	☐	☐
Security	RISAB	RISAB1	☑^OP-TEE	⬚	☐	⬚
		RISAB2	☑^OP-TEE	⬚	☐	⬚
		RISAB3	☑^OP-TEE	⬚	☐	⬚
		RISAB4	☑^OP-TEE	⬚	☐	⬚
		RISAB5	☑^OP-TEE	⬚	☐	⬚
		RISAB6	☑^OP-TEE	⬚	☐	⬚
Security	RISAF	RISAF1	☑^OP-TEE	⬚	☐	⬚		OP-TEE configures all regions
		RISAF2	☑^OP-TEE	⬚	☐	⬚		OP-TEE configures all regions
		RISAF4	☑^OP-TEE	⬚	☐	⬚		OP-TEE configures all regions except its own
		RISAF5	☑^OP-TEE	⬚	☐	⬚		OP-TEE configures all regions
Security	IAC	IAC	✓^OP-TEE		⬚			Fixed to TDCID
Trace & Debug	SERC	SERC	☑^OP-TEE	⬚
Trace & Debug	HDP	HDP	⬚^OP-TEE	☑	⬚	⬚
Trace & Debug	DDRPERFM	DDRPERFM	⬚^OP-TEE	☐	⬚	⬚
Visual	GPU	GPU	⬚^OP-TEE	☑	⬚	⬚
Visual	DSI	DSI	☐^OP-TEE	☐	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Visual	LTDC	LTDC	☐^OP-TEE	☐	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the runtime allocation per feature
Visual	DCMI	DCMI	⬚^OP-TEE	☑	⬚	☐
Visual	CSI	CSI	⬚^OP-TEE	☑	⬚	☐
Visual	LVDS	LVDS	⬚^OP-TEE	☑	⬚	☐
Visual	DCMIPP	DCMIPP	⬚^OP-TEE	☑	⬚	☐
Visual	VENC	VENC	⬚^OP-TEE	☑	⬚	⬚
Visual	VDEC	VDEC	⬚^OP-TEE	☑	⬚	⬚

3. Internal peripherals boot time assignment[edit | edit source]↑

Click on to expand or collapse the legend...

ADF internal peripheral ETHSW internal peripheral

Domain	Peripheral	Boot time allocation				Comment
Domain	Peripheral	Instance	Cortex-A35 secure (ROM code)	Cortex-A35 secure (TF-A BL2)	Cortex-A35 non-secure (U-Boot)	Comment
Core/Processors	Arm^® Cortex^®-A35	Arm^® Cortex^®-A35	✓	✓	✓
Core/Processors	Arm^® Cortex^®-M33 (coprocessor)	Arm^® Cortex^®-M33 (coprocessor)		⬚	☐	How to start the coprocessor from the bootloader How_to_protect_the_coprocessor_firmware
Core/Processors	Arm^® Cortex^®-M0+ (coprocessor)	Arm^® Cortex^®-M0+		⬚	☐
Analog	VREFBUF	VREFBUF			☐
Analog	ADC	ADC12		⬚	☐
Analog	ADC	ADC3		⬚	☐
Analog	MDF	MDF1			⬚
Low speed interface or audio	SPI	SPI2S1		⬚	☐
		SPI2S2		⬚	☐
		SPI2S3		⬚	☐
		SPI4		⬚	☐
		SPI5		⬚	☐
		SPI6		⬚	☐
		SPI7		⬚	☐
		SPI8		⬚	☐
Audio	SPDIFRX	SPDIFRX			⬚
Audio	SAI	SAI1			⬚
		SAI2			⬚
		SAI3			⬚
		SAI4			⬚
Coprocessor	IPCC	IPCC1		⬚	⬚	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Coprocessor	IPCC	IPCC2		⬚	⬚	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core	SYSCFG	SYSCFG	✓	☑	☑
Core	STGEN	STGEN	✓	☑	Read-only ^(STGENR)
Core	RTC	RTC		⬚	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core/DMA	HPDMA	HPDMAx (x = 1 to 3)	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core/DMA	LPDMA	LPDMA	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core/Interrupts	EXTI	EXTI1	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core/Interrupts	EXTI	EXTI2	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core/Interrupts	GIC	GIC		⬚	⬚
Core/IOs	GPIO	GPIOA-K	✓	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core/IOs	GPIO	GPIOZ		☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Core/RAM	DDRCTRL	DDR		☑	⬚
Core/RAM	BKPSRAM	BKPSRAM		☑	⬚
Core/Timers	TIM	TIMx (x = 1 to 8, 10 to 17, 20)		⬚	⬚
Core/Timers	LPTIM	LPTIMx (x = 1 to 5)		⬚	⬚	LPTIM are not used at boot time.
Core/Watchdog	IWDG	IWDG1	✓	☑	☐
		IWDG2	✓	☐	☑
		IWDG3
		IWDG4
		IWDG5
High speed interface	USB3DR	USB3DR	☐	☐	☐	The USB3DR can be used by ROM code, FSBL and SSBL in DFU mode to support serial boot. It can be used also in U-boot with command line tools.
High speed interface	USBH	USBH		⬚	☐
High speed interface	COMBOPHY	COMBOPHY			☐
High speed interface	UCPD	UCPD1		⬚	⬚
High speed interface	USB2PHY	USB2PHY1	⬚	⬚	☐	USB2PHY1 can be used in U-boot by USBH with command line tools.
High speed interface	USB2PHY	USB2PHY2	☐	☐	☐	USB2PHY2 can be used by ROM code, FSBL and SSBL in DFU mode to support serial boot. It can be used also in U-boot by USB3DR with command line tools.
High speed interface	PCIe	PCIe			☐	The PCIe and the USB3DR running at USB3 speed are mutually exclusive. Both require to use the ComboPHY.
Low speed interface	USART	UART4	☐	☐	☐
		UART5	☐	☐	☐
		UART7	☐	☐	☐
		UART8	☐	☐	☐
		UART9	☐	☐	☐
		USART1	☐	☐	☐
		USART2	☐	☐	☐
		USART3	☐	☐	☐
		USART6	☐	☐	☐
Low speed interface	I2C	Any instance		☐	☐
Low speed interface	I3C	I3C1		☐	☐
		I3C2		☐	☐
		I3C3		☐	☐
		I3C4		☐	☐
Mass storage	OCTOSPI	OCTOSPI1	☐	☐	☐
Mass storage	OCTOSPI	OCTOSPI2		☐	☐
Mass storage	OCTOSPIM	OCTOSPIM	☐	⬚	☐	TF-A BL2 relies on OCTOSPIM configuration applied by ROM code
Mass storage	FMC	FMC	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Mass storage	SDMMC	SDMMC1	☐	☐	☐
		SDMMC2	☐	☐	☐
		SDMMC3			☐
Networking	FDCAN	FDCAN1			⬚
		FDCAN2			⬚
		FDCAN3			⬚
Power & Thermal	RCC	RCC	✓	✓	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Power & Thermal	PWR	PWR	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Power & Thermal	DTS	DTS			⬚
Security	BSEC	BSEC	✓	✓
Security	HASH	HASH	✓	☑	☐
Security	CRYP	CRYP1	☑	☑	⬚	ROM code allocation is managed with the bit 8 in OTP 16
Security	CRYP	CRYP2			⬚
Security	SAES	SAES	☐	☑	⬚	ROM code allocation is managed with the bit 8 in OTP 16
Security	TAMP	TAMP	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Security	OTFDEC	OTFDEC1		⬚	⬚
Security	OTFDEC	OTFDEC2		⬚	⬚
Security	PKA	PKA	✓	☑	⬚	Assignment is mandatory only for secure boot
Security	RIFSC	RIFSC	✓	☑	☑
Security	RISAB	RISAB1	✓	✓	⬚
		RISAB2	✓	✓	⬚
		RISAB3	✓	⬚	⬚	Used by ROM code only in serial boot for USB buffer management
		RISAB4		⬚	⬚
		RISAB5	✓	⬚	⬚	Used by ROM code only during cold boot
		RISAB6		⬚	⬚
Security	RISAF	RISAF1		☐	⬚
		RISAF2		☐	⬚
		RISAF4		☑	⬚	FSBL TF-A configures Cortex-A secure and encrypted memory regions
		RISAF5		☐	⬚
Security	IAC	IAC		⬚		Fixed to TDCID
Trace & Debug	SERC	SERC		⬚
Trace & Debug	DBGMCU	DBGMCU	⬚	⬚	⬚
Trace & Debug	HDP	HDP		⬚	⬚
Trace & Debug	DDRPERFM	DDRPERFM		⬚	⬚
Visual	GPU	GPU			⬚
Visual	DSI	DSI	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Visual	LTDC	LTDC	☐	☐	☐	Shareable at internal peripheral level thanks to the RIF: see the boot time allocation per feature
Visual	DCMI	DCMI			⬚
Visual	CSI	CSI			⬚
Visual	LVDS	LVDS			☑
Visual	DCMIPP	DCMIPP			⬚
Visual	VENC	VENC			⬚
Visual	VDEC	VDEC			⬚

4. References[edit | edit source]↑

[1] STM32 MPU microprocessor devices: multiple-core architecture concepts

[2] STM32MP25 reference manuals

[1]

[2]

@@ Line 36: / Line 36: @@
 rect 12 10 152 60 [[Arm Cortex-A35 | Cortex-A35]]
 rect 702 11 841 61 [[Arm Cortex-M33 | Cortex-M33]]
-rect 10 83 77 105 [[Arm CoreSight internal peripherals | Arm CoreSight ]]
+rect 10 83 77 105 [[STGEN internal peripheral | STGEN]]
 rect 10 111 77 133 [[SYSCFG internal peripheral | SYSCFG]]
 rect 10 138 77 160 [[RTC internal peripheral | RTC]]
@@ Line 101: / Line 101: @@
 rect 465 323 531 345 [[ETHSW internal peripheral | ETHSW]]
 rect 549 323 616 345 [[DBGMCU internal peripheral | DBGMCU]]
-rect 549 351 616 374 [[Arm CoreSight overview | Arm CoreSight peripherals]]
+rect 549 351 616 374 [[Arm CoreSight internal peripherals | Arm CoreSight]]
 rect 622 323 689 345 [[HDP internal peripheral | HDP]]
 rect 623 351 690 374 [[SERC internal peripheral | SERC]]
@@ Line 130: / Line 130: @@
 {{#lst:HSEM_internal_peripheral|stm32mp25_a35_runtime}}
 {{#lst:SYSCFG_internal_peripheral|stm32mp25_a35_runtime}}
+{{#lst:STGEN_internal_peripheral|stm32mp25_a35_runtime}}
 {{#lst:RTC_internal_peripheral|stm32mp25_a35_runtime}}
 {{#lst:HPDMA internal peripheral|stm32mp25_a35_runtime}}
@@ Line 209: / Line 210: @@
 {{#lst:HSEM_internal_peripheral|stm32mp25_a35_boottime}}
 {{#lst:SYSCFG_internal_peripheral|stm32mp25_a35_boottime}}
+{{#lst:STGEN_internal_peripheral|stm32mp25_a35_boottime}}
 {{#lst:RTC_internal_peripheral|stm32mp25_a35_boottime}}
 {{#lst:HPDMA internal peripheral|stm32mp25_a35_boottime}}