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<noinclude>{{ApplicableFor
<noinclude>{{ApplicableFor
|MPUs list=STM32MP13x, STM32MP15x
|MPUs list=STM32MP13x, STM32MP15x, STM32MP25x
|MPUs checklist=STM32MP13x,STM32MP15x
|MPUs checklist=STM32MP13x,STM32MP15x, STM32MP25x
}}</noinclude>
}}</noinclude>
==Article purpose==
==Article purpose==
The purpose of this article is to
The purpose of this article is to:
* briefly introduce the USBH peripheral and its main features
* briefly introduce the USBH peripheral and its main features,
* indicate the level of security supported by this hardware block
* indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
* explain how it can be allocated to the runtime contexts and linked to the corresponding software components
* list the software frameworks and drivers managing the peripheral,
* explain, when needed, how to configure the USBH peripheral.
* explain how to configure the peripheral.


==Peripheral overview==
==Peripheral overview==
The '''USBH''' peripheral is used to interconnect other systems with STM32 MPU devices, using USB standard.
The '''USBH''' peripheral is used to interconnect other systems with STM32 MPU devices, using USB standard.


===Features===
The '''USBH''' peripheral is a USB Host controller supporting high-speed (480 Mbit/s) using an '''EHCI''' controller, and full- and low- speeds (12 and 1.5 Mbit/s) through '''OHCI''' controller. <br>
The '''USBH''' peripheral is a USB Host controller supporting high-speed (480 Mbit/s) using an '''EHCI''' controller, and full- and low- speeds (12 and 1.5 Mbit/s) through '''OHCI''' controller. <br>
The '''USBH''' peripheral has two physical ports providing a '''UTMI+''' physical interface, mapped on an on-chip 2-port '''[[USBPHYC internal peripheral|high-speed UTMI+ PHY]]'''. <br>
The '''USBH''' peripheral supports the following PHY interfaces:
{| class="st-table"
|- style="background: {{STLightGrey}};"
! style="width:40%;  | SoC
! style="width:20%;  | Number of physical ports (UTMI+)
! style="width:20%;" | USBH peripheral PHY interfaces
|-
| {{MicroprocessorDevice | device=1}}
| 2
| [[USBPHYC internal peripheral|USBPHYC internal peripheral]]
|-
| {{MicroprocessorDevice | device=2}}
| 1
| [[USB2PHY_internal_peripheral|USB2PHY internal peripheral]]
|-
|}
It supports the standard registers used for low- and full-speed operation ('''OHCI''' model) and high-speed operation ('''EHCI''' model) and the power management feature called Link Power Management (LPM).
It supports the standard registers used for low- and full-speed operation ('''OHCI''' model) and high-speed operation ('''EHCI''' model) and the power management feature called Link Power Management (LPM).


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* ''EHCI v1.1 Addendum''<ref name="ehci_addendum">[https://www.intel.com/content/www/us/en/io/universal-serial-bus/ehci-v1-1-addendum.html Enhanced Host Controller Interface Specification: Addendum]</ref>, August 2008
* ''EHCI v1.1 Addendum''<ref name="ehci_addendum">[https://www.intel.com/content/www/us/en/io/universal-serial-bus/ehci-v1-1-addendum.html Enhanced Host Controller Interface Specification: Addendum]</ref>, August 2008
* ''Open Host Controller Interface Specification for USB''<ref name="ohci_specification">[https://www.usb.org Open Host Controller Interface Specification for USB]</ref>, Release 1.0a, September 14, 1999
* ''Open Host Controller Interface Specification for USB''<ref name="ohci_specification">[https://www.usb.org Open Host Controller Interface Specification for USB]</ref>, Release 1.0a, September 14, 1999
* ''USB 2.0 Transceiver Macrocell Interface (UTMI) Specification''<ref name="utmi_specification">[https://www.intel.com/content/www/us/en/io/universal-serial-bus/usb2-transceiver-macrocell-interface-specification.html USB 2.0 Transceiver Macrocell Interface (UTMI) Specification]</ref>, Version 1.05, March 29, 2001
* ''USB 2.0 Transceiver Macrocell Interface (UTMI) Specification''<ref name="utmi_specification">[https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/usb2-transceiver-macrocell-interface-specifications.pdf USB 2.0 Transceiver Macrocell Interface (UTMI) Specification]</ref>, Version 1.05, March 29, 2001
* ''UTMI+ Specification''<ref name="utmi+_specification">[https://www.nxp.com/docs/en/brochure/UTMI-PLUS-SPECIFICATION.pdf UTMI+ Specification]</ref>, Revision 1.0, February 25, 2004
* ''UTMI+ Specification''<ref name="utmi+_specification">[https://www.nxp.com/docs/en/brochure/UTMI-PLUS-SPECIFICATION.pdf UTMI+ Specification]</ref>, Revision 1.0, February 25, 2004


Refer to [[STM32MP13 resources#Reference manuals|STM32MP13 reference manuals]] or [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete features list, and to the software components, introduced below, to know which features are really implemented.
Refer to the [[STM32 MPU resources#Reference manuals|STM32 MPU reference manuals]] for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.


===Security support===
==Peripheral usage==
The '''USBH''' peripheral is a '''non-secure''' peripheral.
This chapter is applicable in the scope of the '''OpenSTLinux BSP''' running on the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A processor(s), and the '''STM32CubeMPU Package''' running on the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M processor.


==Peripheral usage and associated software==
===Boot time assignment===
===Boot time===
====On {{MicroprocessorDevice | device=1}}====
The '''USBH''' peripheral is usually not used at boot time. But it may be used by the SSBL (see [[Boot chain overview]]), for example to boot a kernel stored on a USB key (mass storage).
The '''USBH''' peripheral is usually not used at boot time. But it may be used by the SSBL (see [[Boot chain overview]]), for example to boot a kernel stored on a USB key (mass storage).


===Runtime===
{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp1_boottime}}
====Overview====
<section begin=stm32mp13_boottime /><section begin=stm32mp15_boottime />
The '''USBH''' peripheral can be allocated to the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure core to be used under Linux<sup>&reg;</sup> with [[USB overview|USB framework]].
| rowspan="1" | High speed interface
| rowspan="1" | [[USBH internal peripheral|USBH (USB Host)]]
| USBH (USB Host)
|
|
| <span title="assignable peripheral" style="font-size:21px">☐</span>
|
|-
<section end=stm32mp13_boottime /><section end=stm32mp15_boottime />
|}
 
====On {{MicroprocessorDevice | device=2}}====
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp2_a35_boottime}}
<section begin=stm32mp25_a35_boottime />
| rowspan="1" | High speed interface
| rowspan="1" | [[USBH internal peripheral | USBH]]
| USBH
|
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span>
| <span title="assignable peripheral" style="font-size:21px">☐</span>
|
|-
<section end=stm32mp25_a35_boottime />
|}
 
===Runtime assignment===
====On {{MicroprocessorDevice | device=13}}====
{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp13_runtime}}
<section begin=stm32mp13_runtime />
| rowspan="1" | High speed interface
| rowspan="1" | [[USBH internal peripheral|USBH (USB Host)]]
| USBH (USB Host)
|
| <span title="assignable peripheral" style="font-size:21px">☐</span>
|
|-
<section end=stm32mp13_runtime />
|}


====Software frameworks====
====On {{MicroprocessorDevice | device=15}}====
===== On {{MicroprocessorDevice | device=13}} =====
{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp15_runtime}}
{{:STM32MP13 internal peripherals software table template}}
<section begin=stm32mp15_runtime />
| High speed interface
| rowspan="1" | High speed interface
| [[USBH internal peripheral|USBH (USB Host)]]
| rowspan="1" | [[USBH internal peripheral|USBH (USB Host)]]
|  
| USBH (USB Host)
| [[USB overview | Linux USB framework]]
|  
|
| <span title="assignable peripheral" style="font-size:21px">☐</span>
|-
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span>
|}
|
===== On {{MicroprocessorDevice | device=15}} =====
|-
{{:Internal_peripherals_software_table_template}}
<section end=stm32mp15_runtime />
| High speed interface
|}
| [[USBH internal peripheral|USBH (USB Host)]]
|
| [[USB overview | Linux USB framework]]
|
|
|-
|}


====Peripheral configuration====
====On {{MicroprocessorDevice | device=25}}====
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be performed via the [[STM32CubeMX]] tool for all internal peripherals. It can then be manually completed (especially for external peripherals) according to the information given in the corresponding software framework article.
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp25_runtime}}
<section begin=stm32mp25_a35_runtime />
| rowspan="1" | High speed interface
| rowspan="1" | [[USBH internal peripheral | USBH]]
| USBH
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span><sup>OP-TEE</sup>
| <span title="assignable peripheral" style="font-size:21px">☐</span>
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span>
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span>
|
|
|-
<section end=stm32mp25_a35_runtime />
|}


For Linux kernel configuration, please refer to [[USBH device tree configuration|USBH device tree configuration]].
==Software frameworks and drivers==
Below are listed the software frameworks and drivers managing the USBH peripheral for the embedded software components listed in the above tables.


====Peripheral assignment====
* '''Linux<sup>&reg;</sup>''': [[USB overview|USB framework]]
===== On {{MicroprocessorDevice | device=13}} =====
* '''U-Boot''': USB framework ({{CodeSource | U-Boot | common/usb.c}}) and drivers ({{CodeSource | U-Boot | drivers/usb/host/ehci-generic.c | ehci-generic.c}}, {{CodeSource | U-Boot | drivers/usb/host/ohci-generic.c | ohci-generic.c}})
{{:STM32MP13_internal_peripherals_assignment_table_template}}
 
<section begin=stm32mp13 />
==How to assign and configure the peripheral==
| rowspan="1" | High speed interface
The peripheral assignment can be done via the [[STM32CubeMX]] graphical tool (and manually completed if needed).<br />
| rowspan="1" | [[USBH internal peripheral|USBH (USB Host)]]
This tool also helps to configure the peripheral:
| USBH (USB Host)
* partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
|  
* HAL initialization code generation for the STM32CubeMPU Package.
| <span title="assignable peripheral" style="font-size:21px">☐</span>
The configuration is applied by the firmware running in the context in which the peripheral is assigned.
|
 
|-
For Linux kernel and U-boot configuration, please refer to [[USBH device tree configuration|USBH device tree configuration]].
<section end=stm32mp13 />
|}
===== On {{MicroprocessorDevice | device=15}} =====
{{:Internal_peripherals_assignment_table_template}}
<section begin=stm32mp15 />
| rowspan="1" | High speed interface
| rowspan="1" | [[USBH internal peripheral|USBH (USB Host)]]
| USBH (USB Host)
|
| <span title="assignable peripheral" style="font-size:21px">☐</span>
|
|
|-
<section end=stm32mp15 />
|}


==References==
==References==
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<noinclude>
<noinclude>
[[Category:High speed interface peripherals]]
[[Category:High speed interface peripherals]]
{{ArticleBasedOnModel | Internal peripheral article model}}
{{PublicationRequestId | 8440 | 2018-09-20 | BrunoB}}
{{PublicationRequestId | 8440 | 2018-09-20 | BrunoB}}
{{ArticleBasedOnModel | Internal peripheral article model}}
{{ReviewsComments|JCT 1840: alignment needed with the last version of the model<br>
[[Category:ToBeAlignedWithModel]]
}}
</noinclude>
</noinclude>

Latest revision as of 17:07, 8 November 2024↑

Applicable for STM32MP13x lines, STM32MP15x lines, Unknown MPU

1. Article purpose↑

The purpose of this article is to:

  • briefly introduce the USBH peripheral and its main features,
  • indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
  • list the software frameworks and drivers managing the peripheral,
  • explain how to configure the peripheral.

2. Peripheral overview↑

The USBH peripheral is used to interconnect other systems with STM32 MPU devices, using USB standard.

The USBH peripheral is a USB Host controller supporting high-speed (480 Mbit/s) using an EHCI controller, and full- and low- speeds (12 and 1.5 Mbit/s) through OHCI controller.
The USBH peripheral supports the following PHY interfaces:

SoC Number of physical ports (UTMI+) USBH peripheral PHY interfaces
STM32MP1 Series 2 USBPHYC internal peripheral
STM32MP2 unknown microprocessor device 1 USB2PHY internal peripheral

It supports the standard registers used for low- and full-speed operation (OHCI model) and high-speed operation (EHCI model) and the power management feature called Link Power Management (LPM).

The supported standards are:

  • Universal Serial Bus Revision 2.0 Specification[1], Revision 2.0, April 27, 2000
  • USB 2.0 Link Power Management Addendum Engineering Change Notice to the USB 2.0 specification[2], July 16, 2007
  • Enhanced Host Controller Interface Specification for Universal Serial Bus[3], Revision 1.0, March 12, 2002
  • EHCI v1.1 Addendum[4], August 2008
  • Open Host Controller Interface Specification for USB[5], Release 1.0a, September 14, 1999
  • USB 2.0 Transceiver Macrocell Interface (UTMI) Specification[6], Version 1.05, March 29, 2001
  • UTMI+ Specification[7], Revision 1.0, February 25, 2004

Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.

3. Peripheral usage↑

This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm® Cortex®-A processor(s), and the STM32CubeMPU Package running on the Arm® Cortex®-M processor.

3.1. Boot time assignment↑

3.1.1. On STM32MP1 Series↑

The USBH peripheral is usually not used at boot time. But it may be used by the SSBL (see Boot chain overview), for example to boot a kernel stored on a USB key (mass storage).


Click on How to.png to expand or collapse the legend...

Domain Peripheral Boot time allocation Comment How to.png
Instance Cortex-A7
secure
(ROM code) 		Cortex-A7
secure
(TF-A BL2) 		Cortex-A7
non-secure
(U-Boot)
High speed interface USBH (USB Host) USBH (USB Host) ☐

3.1.2. On STM32MP2 unknown microprocessor device↑

Click on How to.png to expand or collapse the legend...

Domain Peripheral Boot time allocation Comment How to.png
Instance Cortex-A35
secure
(ROM code) 		Cortex-A35
secure
(TF-A BL2) 		Cortex-A35
non-secure
(U-Boot)
High speed interface USBH USBH ⬚ ☐

3.2. Runtime assignment↑

3.2.1. On STM32MP13x lines More info.png↑

Click on How to.png to expand or collapse the legend...

Domain Peripheral Runtime allocation Comment How to.png
Instance Cortex-A7
secure
(OP-TEE) 		Cortex-A7
non-secure
(Linux)
High speed interface USBH (USB Host) USBH (USB Host) ☐

3.2.2. On STM32MP15x lines More info.png↑

Click on How to.png to expand or collapse the legend...

Domain Peripheral Runtime allocation Comment How to.png
Instance Cortex-A7
secure
(OP-TEE) 		Cortex-A7
non-secure
(Linux) 		Cortex-M4

(STM32Cube)
High speed interface USBH (USB Host) USBH (USB Host) ☐ ⬚

3.2.3. On STM32MP25 unknown microprocessor device↑

Click on How to.png to expand or collapse the legend...

Domain Peripheral Runtime allocation Comment How to.png
Instance Cortex-A35
secure
(OP-TEE /
TF-A BL31) 		Cortex-A35
non-secure
(Linux) 		Cortex-M33
secure
(TF-M) 		Cortex-M33
non-secure
(STM32Cube) 		Cortex-M0+
Warning.png
(STM32Cube)
High speed interface USBH USBH ⬚OP-TEE ☐ ⬚ ⬚

4. Software frameworks and drivers↑

Below are listed the software frameworks and drivers managing the USBH peripheral for the embedded software components listed in the above tables.

5. How to assign and configure the peripheral↑

The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:

  • partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
  • HAL initialization code generation for the STM32CubeMPU Package.

The configuration is applied by the firmware running in the context in which the peripheral is assigned.

For Linux kernel and U-boot configuration, please refer to USBH device tree configuration.

6. References↑

  1. ↑ Universal Serial Bus Revision 2.0 Specification
  2. ↑ ECN USB 2.0 Link Power Management Addendum
  3. ↑ Enhanced Host Controller Interface Specification for Universal Serial Bus
  4. ↑ Enhanced Host Controller Interface Specification: Addendum
  5. ↑ Open Host Controller Interface Specification for USB
  6. ↑ USB 2.0 Transceiver Macrocell Interface (UTMI) Specification
  7. ↑ UTMI+ Specification


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