Registered User mNo edit summary |
Registered User m (Oxford comma. Compound numbers are always hyphenated. "allows" requires an object before an infinitive verb or the usage of a passive construction. "run time" is deprecated ==> "runtime". Trademark for CoreSight™ and microSD. Mhz to MHz.) Tag: 2017 source edit |
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__FORCETOC__ | __FORCETOC__ | ||
All the peripherals receive one or several clocks that are generated via [[RCC internal peripheral]]. RCC relies on several clocks sources (LSI, LSE, HSI, HSE, MSI), height PLL and sixty four FLEXGEN | All the peripherals receive one or several clocks that are generated via [[RCC internal peripheral]]. RCC relies on several clocks sources (LSI, LSE, HSI, HSE, MSI), height PLL, and sixty-four FLEXGEN in order to provide adequate input frequencies to all the peripherals. The clock tree covers all the system clock distribution aspects, from the clock sources to the consumer peripherals (internal and external), except clock gating management that is locally controlled by each peripheral driver. | ||
== Overview == | == Overview == | ||
| Line 12: | Line 12: | ||
* The [[STM32 MPU ROM code overview|ROM Code]] configures the minimum clock tree needed to boot on the selected boot device. | * The [[STM32 MPU ROM code overview|ROM Code]] configures the minimum clock tree needed to boot on the selected boot device. | ||
* [[TF-A overview|TF-A BL2]] has the same strategy as the ROM code, configuring the minimum clock tree needed for its execution, thanks to the configuration given in the [[STM32 MPU device tree|device tree]]. | * [[TF-A overview|TF-A BL2]] has the same strategy as the ROM code, configuring the minimum clock tree needed for its execution, thanks to the configuration given in the [[STM32 MPU device tree|device tree]]. | ||
* [[OP-TEE overview|OP-TEE]] completely configures the clock tree as expected, all the way up to Linux, thanks to the configuration given in the [[STM32 MPU device tree|device tree]]. | * [[STM32 MPU OP-TEE overview|OP-TEE]] completely configures the clock tree as expected, all the way up to Linux, thanks to the configuration given in the [[STM32 MPU device tree|device tree]]. | ||
* '''Linux''' may partly modify clock tree at runtime thanks to [[SCMI overview|SCMI]] clock services provided by [[OP-TEE overview|OP-TEE]] secure OS. Information related to [[SCMI overview|SCMI]] are taken from the [[STM32 MPU device tree|device tree]]: | * '''Linux''' may partly modify clock tree at runtime thanks to [[SCMI overview|SCMI]] clock services provided by [[STM32 MPU OP-TEE overview|OP-TEE]] secure OS. Information related to [[SCMI overview|SCMI]] are taken from the [[STM32 MPU device tree|device tree]]: | ||
** Linux binding is available in {{CodeSource | Linux kernel | Documentation/devicetree/bindings/clock/clock-bindings.txt | Documentation/devicetree/bindings/clock/clock-bindings.txt}} (and surrounding files): 'fixed-clock' compatible, 'clocks' and 'assigned-clocks' properties are important concepts to understand the management of clocks providers/consumers. | ** Linux binding is available in {{CodeSource | Linux kernel | Documentation/devicetree/bindings/clock/clock-bindings.txt | Documentation/devicetree/bindings/clock/clock-bindings.txt}} (and surrounding files): 'fixed-clock' compatible, 'clocks' and 'assigned-clocks' properties are important concepts to understand the management of clocks providers/consumers. | ||
==How to build a clock tree | ==How to build a clock tree== | ||
Building a clock tree is quite complex as it needs to take into account the constraints set by each internal and external peripheral, including external clock sources. | Building a clock tree is quite complex as it needs to take into account the constraints set by each internal and external peripheral, including external clock sources. | ||
We encourage the use of [[STM32CubeMX]] to build the clock tree, and avoid having to know all internal peripherals details: the tool allows | We encourage the use of [[STM32CubeMX]] to build the clock tree, and avoid having to know all internal peripherals details: the tool allows the selection of the peripherals that will be present on the board, fix the clock sources frequencies and automatically find an optimized clock tree. It is then able to generate the device tree that is directly consumed by the boot chain and the secure OS. Linux kernel will be able to modify clock tree at runtime thanks to [[SCMI overview|SCMI]] clock services provided by [[STM32 MPU OP-TEE overview|OP-TEE]]. | ||
==ST boards clock tree== | ==ST boards clock tree== | ||
| Line 26: | Line 26: | ||
{{Info|See [[How to change the CPU frequency]] article for more information about the CPU frequency setting (PLL1), including dynamic voltage and frequency scaling (DVFS) configuration.}} | {{Info|See [[How to change the CPU frequency]] article for more information about the CPU frequency setting (PLL1), including dynamic voltage and frequency scaling (DVFS) configuration.}} | ||
==={{Board | type=257F-EV1}} case=== | ==={{Board | type=257F-EV1}} case=== | ||
This chapter shows the result of the boot time clock tree set by the FSBL, overlaid by the | This chapter shows the result of the boot time clock tree set by the FSBL, overlaid by the runtime clock tree set by the Secure OS on {{Board | type=257F-EV1}}. | ||
Linux eventual runtime modifications are not covered here. | Linux eventual runtime modifications are not covered here. | ||
| Line 92: | Line 92: | ||
BSEC |APB5 | 66.625000 MHz | yes | < 67MHz | BSEC |APB5 | 66.625000 MHz | yes | < 67MHz | ||
ETZPC |APB5 | 66.625000 MHz | yes | | ETZPC |APB5 | 66.625000 MHz | yes | | ||
DBGAPB |AXI | 133.250000 MHz | yes | JTAG & | DBGAPB |AXI | 133.250000 MHz | yes | JTAG & CoreSight™ | ||
DBGMCU |DBGAPB | 66.625000 MHz | yes | | DBGMCU |DBGAPB | 66.625000 MHz | yes | | ||
PLL2Q |PLL2 | 266.500000 MHz | yes | | PLL2Q |PLL2 | 266.500000 MHz | yes | | ||
| Line 154: | Line 154: | ||
ETH1 |PLL4P | 50.000000 MHz | yes | 50MHz from the SoC | ETH1 |PLL4P | 50.000000 MHz | yes | 50MHz from the SoC | ||
ETH2 |PLL4P | 50.000000 MHz | yes | 50MHz from the SoC | ETH2 |PLL4P | 50.000000 MHz | yes | 50MHz from the SoC | ||
SDMMC1 |PLL4P | 50.000000 MHz | yes | | SDMMC1 |PLL4P | 50.000000 MHz | yes | microSD™ card | ||
SDMMC2 |PLL4P | 50.000000 MHz | yes | Wifi | SDMMC2 |PLL4P | 50.000000 MHz | yes | Wifi | ||
SPI1 |PLL4P | 50.000000 MHz | no | | SPI1 |PLL4P | 50.000000 MHz | no | | ||
| Line 208: | Line 208: | ||
pll1: st,pll@0 { | pll1: st,pll@0 { | ||
st,pll = <& | st,pll = <&pll1_cfg_1200MHz>; | ||
pll1_cfg_1200MHz: pll1-cfg-1200MHz { | |||
cfg = <30 1 1 1>; | cfg = <30 1 1 1>; | ||
src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>; | src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>; | ||
| Line 218: | Line 218: | ||
/* DRAM clock = 2 * PLL2 clock */ | /* DRAM clock = 2 * PLL2 clock */ | ||
pll2: st,pll@1 { | pll2: st,pll@1 { | ||
st,pll = <& | st,pll = <&pll2_cfg_600MHz>; | ||
pll2_cfg_600MHz: pll2-cfg-600MHz { | |||
cfg = <30 1 1 2>; | cfg = <30 1 1 2>; | ||
src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>; | src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>; | ||
| Line 227: | Line 227: | ||
pll4: st,pll@3 { | pll4: st,pll@3 { | ||
st,pll = <& | st,pll = <&pll4_cfg_1200MHz>; | ||
pll4_cfg_1200MHz: pll4-cfg-1200MHz { | |||
cfg = <30 1 1 1>; | cfg = <30 1 1 1>; | ||
src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>; | src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>; | ||
| Line 236: | Line 236: | ||
pll5: st,pll@4 { | pll5: st,pll@4 { | ||
st,pll = <& | st,pll = <&pll5_cfg_532MHz>; | ||
pll5_cfg_532MHz: pll5-cfg-532MHz { | |||
cfg = <133 5 1 2>; | cfg = <133 5 1 2>; | ||
src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>; | src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>; | ||
| Line 342: | Line 342: | ||
pll1: st,pll@0 { | pll1: st,pll@0 { | ||
st,pll = <& | st,pll = <&pll1_cfg_1200MHz>; | ||
pll1_cfg_1200MHz: pll1-cfg-1200MHz { | |||
cfg = <30 1 1 1>; | cfg = <30 1 1 1>; | ||
src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>; | src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>; | ||
}; | }; | ||
pll1_cfg_1500MHz: pll1-cfg-1500MHz { | |||
cfg = <75 2 1 1>; | cfg = <75 2 1 1>; | ||
src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>; | src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>; | ||
| Line 356: | Line 356: | ||
pll2: st,pll@1 { | pll2: st,pll@1 { | ||
st,pll = <& | st,pll = <&pll2_cfg_600MHz>; | ||
pll2_cfg_600MHz: pll2-cfg-600MHz { | |||
cfg = <30 1 1 2>; | cfg = <30 1 1 2>; | ||
src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>; | src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>; | ||
| Line 365: | Line 365: | ||
pll3: st,pll@2 { | pll3: st,pll@2 { | ||
st,pll = <& | st,pll = <&pll3_cfg_800MHz>; | ||
pll3_cfg_800MHz: pll3-cfg-800MHz { | |||
cfg = <20 1 1 1>; | cfg = <20 1 1 1>; | ||
src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>; | src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>; | ||
}; | }; | ||
pll3_cfg_900MHz: pll3-cfg-900MHz { | |||
cfg = <45 2 1 1>; | cfg = <45 2 1 1>; | ||
src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>; | src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>; | ||
| Line 379: | Line 379: | ||
pll4: st,pll@3 { | pll4: st,pll@3 { | ||
st,pll = <& | st,pll = <&pll4_cfg_1200MHz>; | ||
pll4_cfg_1200MHz: pll4-cfg-1200MHz { | |||
cfg = <30 1 1 1>; | cfg = <30 1 1 1>; | ||
src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>; | src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>; | ||
| Line 388: | Line 388: | ||
pll5: st,pll@4 { | pll5: st,pll@4 { | ||
st,pll = <& | st,pll = <&pll5_cfg_532MHz>; | ||
pll5_cfg_532MHz: pll5-cfg-532MHz { | |||
cfg = <133 5 1 2>; | cfg = <133 5 1 2>; | ||
src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>; | src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>; | ||
| Line 397: | Line 397: | ||
pll6: st,pll@5 { | pll6: st,pll@5 { | ||
st,pll = <& | st,pll = <&pll6_cfg_500MHz>; | ||
pll6_cfg_500MHz: pll6-cfg-500MHz { | |||
cfg = <25 1 1 2>; | cfg = <25 1 1 2>; | ||
src = <MUX_CFG(MUX_MUXSEL2, MUXSEL_HSE)>; | src = <MUX_CFG(MUX_MUXSEL2, MUXSEL_HSE)>; | ||
| Line 406: | Line 406: | ||
pll7: st,pll@6 { | pll7: st,pll@6 { | ||
st,pll = <& | st,pll = <&pll7_cfg_835_51172MHz>; | ||
pll7_cfg_835_51172MHz: pll7-cfg-835-51172MHz { | |||
cfg = <167 4 1 2>; | cfg = <167 4 1 2>; | ||
src = <MUX_CFG(MUX_MUXSEL3, MUXSEL_HSE)>; | src = <MUX_CFG(MUX_MUXSEL3, MUXSEL_HSE)>; | ||
| Line 416: | Line 416: | ||
pll8: st,pll@7 { | pll8: st,pll@7 { | ||
st,pll = <& | st,pll = <&pll8_cfg_594MHz>; | ||
pll8_cfg_594MHz: pll8-cfg-594MHz { | |||
cfg = <297 5 1 4>; | cfg = <297 5 1 4>; | ||
src = <MUX_CFG(MUX_MUXSEL4, MUXSEL_HSE)>; | src = <MUX_CFG(MUX_MUXSEL4, MUXSEL_HSE)>; | ||
| Line 425: | Line 425: | ||
}; | }; | ||
</pre> | </pre> | ||
<noinclude> | <noinclude> | ||
[[Category:STM32MP25 platform configuration|0]] | [[Category:STM32MP25 platform configuration|0]] | ||
{{PublicationRequestId | 31760| 2024-07-22| }} | |||
</noinclude> | </noinclude> | ||
Latest revision as of 17:44, 15 August 2024
All the peripherals receive one or several clocks that are generated via RCC internal peripheral. RCC relies on several clocks sources (LSI, LSE, HSI, HSE, MSI), height PLL, and sixty-four FLEXGEN in order to provide adequate input frequencies to all the peripherals. The clock tree covers all the system clock distribution aspects, from the clock sources to the consumer peripherals (internal and external), except clock gating management that is locally controlled by each peripheral driver.
1. Overview
The clock tree is managed via RCC internal peripheral hardware block and it is configured at different steps from the Cortex-A35:
- When the device is reset, all RCC registers take their reset values: the height PLL are disabled and most of the clock source selectors are pointing to the HSI.
- The ROM Code configures the minimum clock tree needed to boot on the selected boot device.
- TF-A BL2 has the same strategy as the ROM code, configuring the minimum clock tree needed for its execution, thanks to the configuration given in the device tree.
- OP-TEE completely configures the clock tree as expected, all the way up to Linux, thanks to the configuration given in the device tree.
- Linux may partly modify clock tree at runtime thanks to SCMI clock services provided by OP-TEE secure OS. Information related to SCMI are taken from the device tree:
- Linux binding is available in Documentation/devicetree/bindings/clock/clock-bindings.txt (and surrounding files): 'fixed-clock' compatible, 'clocks' and 'assigned-clocks' properties are important concepts to understand the management of clocks providers/consumers.
2. How to build a clock tree
Building a clock tree is quite complex as it needs to take into account the constraints set by each internal and external peripheral, including external clock sources.
We encourage the use of STM32CubeMX to build the clock tree, and avoid having to know all internal peripherals details: the tool allows the selection of the peripherals that will be present on the board, fix the clock sources frequencies and automatically find an optimized clock tree. It is then able to generate the device tree that is directly consumed by the boot chain and the secure OS. Linux kernel will be able to modify clock tree at runtime thanks to SCMI clock services provided by OP-TEE.
3. ST boards clock tree
This chapter ensures that all peripherals receive clocks with characteristics compatible with the specification (frequency, duty cycle, precision) on each ST board.
3.1. STM32MP257F-EV1 Evaluation board 
case
This chapter shows the result of the boot time clock tree set by the FSBL, overlaid by the runtime clock tree set by the Secure OS on STM32MP257F-EV1 Evaluation board .
Linux eventual runtime modifications are not covered here.
3.1.1. Clock tree
The following table shows what STM32MP257F-EV1 Evaluation board clock tree looks like, as a result of the boot chain execution with the device tree built with STM32CubeMX.
Component | Parent | Frequency | Used? | Comment |
-----------------------|---------|-----------------|--------|-----------------------------------|
LSI |N.A. | 0.032000 MHz | yes | Mandatory for IWDG, DAC
IWDG1 |LSI | 0.032000 MHz | yes |
IWDG2 |LSI | 0.032000 MHz | yes |
LSE |N.A. | 0.032768 MHz | yes | Mandatory for DTS
RTC |LSE | 0.032768 MHz | yes |
TAMP |LSE | 0.032768 MHz | yes |
DTS |LSE | 0.032768 MHz | yes |
HSI |N.A. | 64.000000 MHz | yes |
I2C1 |HSI | 64.000000 MHz | yes | Rpi and peripherals
I2C2 |HSI | 64.000000 MHz | no |
I2C4 |HSI | 64.000000 MHz | yes | PMIC
I2C5 |HSI | 64.000000 MHz | yes | Rpi and peripherals
USART1 |HSI | 64.000000 MHz | no | Rpi (not used by default)
USART2 |HSI | 64.000000 MHz | yes | Bluetooth
USART3 |HSI | 64.000000 MHz | no |
UART4 |HSI | 64.000000 MHz | yes | Linux console
UART5 |HSI | 64.000000 MHz | no |
USART6 |HSI | 64.000000 MHz | no |
UART7 |HSI | 64.000000 MHz | yes | Arduino
UART8 |HSI | 64.000000 MHz | no | Rpi (not used by default)
HSE |N.A. | 24.000000 MHz | yes |
RTCDIV |HSE | 1.000000 MHz | yes | Only used when RTC source is HSE
USBPHYC |HSE | 24.000000 MHz | yes | USB PHY Ctrl for USB Host and OTG
USBPLL |USBPHYC | 48.000000 MHz | yes |
USBO |USBPLL | 48.000000 MHz | yes | USB OTG
USBH |USBPLL | 48.000000 MHz | yes | USB Host
STGEN |HSE | 24.000000 MHz | yes |
FDCAN2 |HSE | 24.000000 MHz | no | Rpi (not used by default)
ck_per |HSE | 24.000000 MHz | yes |
ADC2 |ck_per | 24.000000 MHz | yes | Analog watchdog
PLL1 |HSE | xxx MHz | yes |
PLL1P |PLL1 | xxx MHz | yes |
MPUDIV |PLL1P | xxx MHz | yes |
Cortex-A7 |PLL1P | xxx MHz | yes | 650 MHz or 1 GHz, see the information box above
PLL2 |HSE | 533.000000 MHz | yes |
PLL2P |PLL2 | 266.500000 MHz | yes |
AXI |PLL2P | 266.500000 MHz | yes | 266.5 MHz
FMC |AXI | 266.500000 MHz | no |
QSPI |AXI | 266.500000 MHz | no |
SAES |AXI | 266.500000 MHz | yes |
TZC |AXI | 266.500000 MHz | yes |
SYSRAM |AXI | 266.500000 MHz | yes |
ROM |AXI | 266.500000 MHz | yes |
AHB5 |AXI | 266.500000 MHz | yes | < 266MHz
CRYP1 |AHB5 | 266.500000 MHz | yes |
HASH1 |AHB5 | 266.500000 MHz | yes |
BKPSRAM |AHB5 | 266.500000 MHz | yes |
PKA |AHB5 | 266.500000 MHz | yes |
AHB6 |AXI | 266.500000 MHz | yes | < 266MHz
CRC1 |AHB6 | 266.500000 MHz | yes |
MDMA |AHB6 | 266.500000 MHz | yes |
MCE |AHB6 | 266.500000 MHz | yes |
APB4 |AXI | 133.250000 MHz | yes | < 133MHz
GPIOA-I |APB4 | 133.250000 MHz | yes |
APB5 |AXI | 66.625000 MHz | yes | < 133MHz
BSEC |APB5 | 66.625000 MHz | yes | < 67MHz
ETZPC |APB5 | 66.625000 MHz | yes |
DBGAPB |AXI | 133.250000 MHz | yes | JTAG & CoreSight™
DBGMCU |DBGAPB | 66.625000 MHz | yes |
PLL2Q |PLL2 | 266.500000 MHz | yes |
DCMIPP |PLL2Q | 266.500000 MHz | yes | < 533MHz
PLL2R |PLL2 | 533.000000 MHz | yes |
DDRPHYC |PLL2R | 533.000000 MHz | yes |
DDRC |PLL2R | 533.000000 MHz | yes |
DDRPERFM |PLL2R | 533.000000 MHz | yes |
PLL3 |HSE | 417.755859 MHz | yes |
PLL3P |PLL3 | 208.877930 MHz | yes |
MLAHB |PLL3P | 208.877930 MHz | yes | < 209MHz
SRAM1 |MLAHB | 208.877930 MHz | yes |
SRAM2 |MLAHB | 208.877930 MHz | yes |
SRAM3 |MLAHB | 208.877930 MHz | yes |
DFSDM |MLAHB | 208.877930 MHz | no | Rpi (not used by default)
AHB1 |MLAHB | 104.438965 MHz | yes | < 104.5MHz
AHB2 |MLAHB | 208.877930 MHz | yes | < 209MHz
DMA1 |AHB2 | 208.877930 MHz | yes |
DMA2 |AHB2 | 208.877930 MHz | yes |
DMA3 |AHB2 | 208.877930 MHz | yes |
DMAMUX1 |AHB2 | 208.877930 MHz | yes |
DMAMUX2 |AHB2 | 208.877930 MHz | yes |
APB1 |MLAHB | 104.438965 MHz | yes |
LPTIM1 |APB1 | 104.438965 MHz | no |
TIMG1 |MLAHB | 208.877930 MHz | yes |
TIM2 |TIMG1 | 208.877930 MHz | no | TIM Group 1
TIM3 |TIMG1 | 208.877930 MHz | no | TIM Group 1 - Rpi (not used by default)
TIM4 |TIMG1 | 208.877930 MHz | no | TIM Group 1 - Rpi (not used by default)
TIM5 |TIMG1 | 208.877930 MHz | no | TIM Group 1
TIM6 |TIMG1 | 208.877930 MHz | no | TIM Group 1
TIM7 |TIMG1 | 208.877930 MHz | no | TIM Group 1
TIMG2 |MLAHB | 208.877930 MHz | yes |
TIM1 |TIMG2 | 208.877930 MHz | no | TIM Group 2
TIM8 |TIMG2 | 208.877930 MHz | no | TIM Group 2 - Rpi (not used by default)
TIMG3 |MLAHB | 208.877930 MHz | yes |
TIM12 |TIMG3 | 208.877930 MHz | no | TIM Group 3
TIM13 |TIMG3 | 208.877930 MHz | no | TIM Group 3
TIM14 |TIMG3 | 208.877930 MHz | no | TIM Group 3 - Rpi (not used by default)
TIM15 |TIMG3 | 208.877930 MHz | no | TIM Group 3
TIM16 |TIMG3 | 208.877930 MHz | no | TIM Group 3
TIM17 |TIMG3 | 208.877930 MHz | no | TIM Group 3
APB3 |MLAHB | 104.438965 MHz | yes |
LPTIM2 |APB3 | 104.438965 MHz | no |
LPTIM3 |APB3 | 104.438965 MHz | yes |
LPTIM4 |APB3 | 104.438965 MHz | no |
LPTIM5 |APB3 | 104.438965 MHz | no |
SYSCFG |APB3 | 104.438965 MHz | yes |
VREFBUF |APB3 | 104.438965 MHz | yes |
HDP |APB3 | 104.438965 MHz | no |
APB6 |MLAHB | 104.438965 MHz | yes |
I2C3 |APB6 | 104.438965 MHz | no |
SPI5 |APB6 | 104.438965 MHz | no | Rpi (not used by default)
AHB4 |MLAHB | 208.877930 MHz | yes | < 209MHz
PWR |AHB4 | 208.877930 MHz | yes |
RCC |AHB4 | 208.877930 MHz | yes |
EXTI |AHB4 | 208.877930 MHz | yes |
PLL3Q |PLL3 | 24.573874 MHz | yes |
PLL3R |PLL3 | 11.290699 MHz | yes |
PLL4 |HSE | 600.000000 MHz | yes |
PLL4P |PLL4 | 50.000000 MHz | yes |
ETH1 |PLL4P | 50.000000 MHz | yes | 50MHz from the SoC
ETH2 |PLL4P | 50.000000 MHz | yes | 50MHz from the SoC
SDMMC1 |PLL4P | 50.000000 MHz | yes | microSD™ card
SDMMC2 |PLL4P | 50.000000 MHz | yes | Wifi
SPI1 |PLL4P | 50.000000 MHz | no |
SPI2 |PLL4P | 50.000000 MHz | no |
SPI3 |PLL4P | 50.000000 MHz | no |
SPDIFRX |PLL4P | 50.000000 MHz | no |
PLL4Q |PLL4 | 10.000000 MHz | yes |
LTDC |PLL4Q | 10.000000 MHz | yes | LTDC display pixel clock
SAI1 |PLL4Q | 10.000000 MHz | no | Rpi (not used by default)
SAI2 |PLL4Q | 10.000000 MHz | no |
SPI4 |PLL4Q | 10.000000 MHz | no |
PLL4R |PLL4 | 50.000000 MHz | yes |
ADC1 |PLL4R | 50.000000 MHz | no |
RNG |PLL4R | 50.000000 MHz | yes |
CSI |N.A. | 4.000000 MHz | yes | Mandatory for IO compensation
-----------------------|---------|-----------------|--------|-----------------------------------|
3.1.2. Device tree
As mentioned in previous chapters, RCC configuration is done in two steps, first by the first stage boot loader (FSBL TF-A) and then by the secure OS (OP-TEE).
Here are the corresponding device tree rcc sub node properties in fdts/stm32mp257f-ev1-ca35tdcid-rcc.dtsi consumed by the first stage boot loader (FSBL TF-A) to configure the clock tree required to boot on STM32MP257F-EV1 Evaluation board :
&rcc {
st,busclk = <
DIV_CFG(DIV_LSMCU, 1)
DIV_CFG(DIV_APB1, 0)
DIV_CFG(DIV_APB2, 0)
DIV_CFG(DIV_APB3, 0)
DIV_CFG(DIV_APB4, 0)
DIV_CFG(DIV_APBDBG, 0)
>;
st,flexgen = <
FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 2)
FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1)
FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3)
FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2)
FLEXGEN_CFG(8, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(48, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(58, XBAR_SRC_HSE, 0, 1)
FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2)
>;
st,kerclk = <
MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57)
MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58)
>;
pll1: st,pll@0 {
st,pll = <&pll1_cfg_1200MHz>;
pll1_cfg_1200MHz: pll1-cfg-1200MHz {
cfg = <30 1 1 1>;
src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
};
};
/* DRAM clock = 2 * PLL2 clock */
pll2: st,pll@1 {
st,pll = <&pll2_cfg_600MHz>;
pll2_cfg_600MHz: pll2-cfg-600MHz {
cfg = <30 1 1 2>;
src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>;
};
};
pll4: st,pll@3 {
st,pll = <&pll4_cfg_1200MHz>;
pll4_cfg_1200MHz: pll4-cfg-1200MHz {
cfg = <30 1 1 1>;
src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>;
};
};
pll5: st,pll@4 {
st,pll = <&pll5_cfg_532MHz>;
pll5_cfg_532MHz: pll5-cfg-532MHz {
cfg = <133 5 1 2>;
src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>;
};
};
};
Here are the corresponding device tree rcc sub node properties in core/arch/arm/dts/stm32mp257f-ev1-ca35tdcid-rcc.dtsi consumed by the secure OS (OP-TEE) to configure the clock tree above:
&rcc {
st,busclk = <
DIV_CFG(DIV_LSMCU, 1)
DIV_CFG(DIV_APB1, 0)
DIV_CFG(DIV_APB2, 0)
DIV_CFG(DIV_APB3, 0)
DIV_CFG(DIV_APB4, 0)
DIV_CFG(DIV_APBDBG, 0)
>;
st,flexgen = <
FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 2)
FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1)
FLEXGEN_CFG(3, XBAR_SRC_PLL4, 0, 2)
FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3)
FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2)
FLEXGEN_CFG(6, XBAR_SRC_PLL4, 0, 1)
FLEXGEN_CFG(7, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(8, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(9, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(10, XBAR_SRC_PLL7, 0, 16)
FLEXGEN_CFG(11, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(12, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(13, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(14, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(15, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(16, XBAR_SRC_PLL4, 0, 23)
FLEXGEN_CFG(17, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(18, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(19, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(20, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(21, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(22, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(23, XBAR_SRC_PLL7, 0, 16)
FLEXGEN_CFG(24, XBAR_SRC_PLL7, 0, 16)
FLEXGEN_CFG(25, XBAR_SRC_PLL7, 0, 16)
FLEXGEN_CFG(26, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(27, XBAR_SRC_PLL8, 0, 3)
FLEXGEN_CFG(28, XBAR_SRC_PLL8, 0, 21)
FLEXGEN_CFG(29, XBAR_SRC_PLL5, 0, 1)
FLEXGEN_CFG(30, XBAR_SRC_HSE, 0, 1)
FLEXGEN_CFG(31, XBAR_SRC_PLL5, 0, 19)
FLEXGEN_CFG(32, XBAR_SRC_PLL5, 0, 19)
FLEXGEN_CFG(33, XBAR_SRC_PLL4, 0, 23)
FLEXGEN_CFG(34, XBAR_SRC_PLL4, 0, 59)
FLEXGEN_CFG(35, XBAR_SRC_HSI, 0, 3)
FLEXGEN_CFG(36, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(37, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(38, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(39, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(40, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(41, XBAR_SRC_PLL4, 0, 11)
FLEXGEN_CFG(42, XBAR_SRC_PLL7, 0, 16)
FLEXGEN_CFG(43, XBAR_SRC_PLL4, 0, 23)
FLEXGEN_CFG(44, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(45, XBAR_SRC_PLL4, 0, 2)
FLEXGEN_CFG(46, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(47, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(48, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(49, XBAR_SRC_PLL5, 0, 3)
FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(53, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(54, XBAR_SRC_PLL6, 0, 3)
FLEXGEN_CFG(55, XBAR_SRC_PLL6, 0, 3)
FLEXGEN_CFG(56, XBAR_SRC_PLL4, 0, 5)
FLEXGEN_CFG(57, XBAR_SRC_HSE, 0, 1)
FLEXGEN_CFG(58, XBAR_SRC_HSE, 0, 1)
FLEXGEN_CFG(59, XBAR_SRC_PLL4, 0, 1)
FLEXGEN_CFG(60, XBAR_SRC_PLL4, 0, 23)
FLEXGEN_CFG(61, XBAR_SRC_PLL4, 0, 7)
FLEXGEN_CFG(62, XBAR_SRC_PLL4, 0, 7)
FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2)
>;
st,kerclk = <
MUX_CFG(MUX_ADC12, MUX_ADC12_FLEX46)
MUX_CFG(MUX_ADC3, MUX_ADC3_FLEX47)
MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57)
MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58)
MUX_CFG(MUX_USB3PCIEPHY, MUX_USB3PCIEPHY_HSE)
MUX_CFG(MUX_DSIPHY, MUX_DSIPHY_FLEX28)
MUX_CFG(MUX_DSIBLANE, MUX_DSIBLANE_DSIPHY)
MUX_CFG(MUX_LVDSPHY, MUX_LVDSPHY_FLEX32)
MUX_CFG(MUX_DTS, MUX_DTS_HSE)
MUX_CFG(MUX_RTC, MUX_RTC_LSE)
MUX_CFG(MUX_D3PER, MUX_D3PER_LSI)
MCO_CFG(MCO1, MUX_MCO1_FLEX61, MCO_OFF)
MCO_CFG(MCO2, MUX_MCO2_FLEX62, MCO_OFF)
>;
pll1: st,pll@0 {
st,pll = <&pll1_cfg_1200MHz>;
pll1_cfg_1200MHz: pll1-cfg-1200MHz {
cfg = <30 1 1 1>;
src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
};
pll1_cfg_1500MHz: pll1-cfg-1500MHz {
cfg = <75 2 1 1>;
src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
};
};
pll2: st,pll@1 {
st,pll = <&pll2_cfg_600MHz>;
pll2_cfg_600MHz: pll2-cfg-600MHz {
cfg = <30 1 1 2>;
src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>;
};
};
pll3: st,pll@2 {
st,pll = <&pll3_cfg_800MHz>;
pll3_cfg_800MHz: pll3-cfg-800MHz {
cfg = <20 1 1 1>;
src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>;
};
pll3_cfg_900MHz: pll3-cfg-900MHz {
cfg = <45 2 1 1>;
src = <MUX_CFG(MUX_MUXSEL7, MUXSEL_HSE)>;
};
};
pll4: st,pll@3 {
st,pll = <&pll4_cfg_1200MHz>;
pll4_cfg_1200MHz: pll4-cfg-1200MHz {
cfg = <30 1 1 1>;
src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>;
};
};
pll5: st,pll@4 {
st,pll = <&pll5_cfg_532MHz>;
pll5_cfg_532MHz: pll5-cfg-532MHz {
cfg = <133 5 1 2>;
src = <MUX_CFG(MUX_MUXSEL1, MUXSEL_HSE)>;
};
};
pll6: st,pll@5 {
st,pll = <&pll6_cfg_500MHz>;
pll6_cfg_500MHz: pll6-cfg-500MHz {
cfg = <25 1 1 2>;
src = <MUX_CFG(MUX_MUXSEL2, MUXSEL_HSE)>;
};
};
pll7: st,pll@6 {
st,pll = <&pll7_cfg_835_51172MHz>;
pll7_cfg_835_51172MHz: pll7-cfg-835-51172MHz {
cfg = <167 4 1 2>;
src = <MUX_CFG(MUX_MUXSEL3, MUXSEL_HSE)>;
frac = < 0x1A3337 >;
};
};
pll8: st,pll@7 {
st,pll = <&pll8_cfg_594MHz>;
pll8_cfg_594MHz: pll8-cfg-594MHz {
cfg = <297 5 1 4>;
src = <MUX_CFG(MUX_MUXSEL4, MUXSEL_HSE)>;
};
};
};