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{{ApplicableFor | |||
|MPUs list=STM32MP15x | |MPUs list=STM32MP15x, STM32MP25x | ||
|MPUs checklist=STM32MP13x, STM32MP15x | |MPUs checklist=STM32MP13x, STM32MP15x, STM32MP25x | ||
}}</noinclude> | }} | ||
<noinclude></noinclude> | |||
This article provides an overview of the management of the heterogeneous asymmetric architecture implemented in the STM32 MPU microprocessor family. It provides information on mechanisms put in place to help developers to design software in the multiprocessor system. | This article provides an overview of the management of the heterogeneous asymmetric architecture implemented in the STM32 MPU microprocessor family. It provides information on mechanisms put in place to help developers to design software in the multiprocessor system. | ||
== System overview== | == System overview== | ||
The STM32 MPU multiprocessor system allows to run independent firmwares on each CPU core. The below subsystems are involved in the management of the coexistence of the two CPU subsystems: | The STM32 MPU multiprocessor system allows to run independent firmwares on each CPU core. The below subsystems are involved in the management of the coexistence of the two CPU subsystems: | ||
* | * An Arm<sup>®</sup> Cortex<sup>®</sup>-A acting as main processor and optimized to run the Linux<sup>®</sup> based OS. | ||
* | * An Arm<sup>®</sup> Cortex<sup>®</sup>-M coprocessor which can run the RTOS optimized for microcontrollers or a bare-metal application. | ||
* [[STM32MP15_RAM_mapping#Memory_mapping| Internal memory regions]] with access granted for both the master and/or the slave processors: | * [[STM32MP15_RAM_mapping#Memory_mapping| Internal memory regions]] with access granted for both the master and/or the slave processors: | ||
** To load and execute coprocessor firmware and define static common structures. | ** To load and execute coprocessor firmware and define static common structures. | ||
| Line 15: | Line 16: | ||
* [[STM32MP15 peripherals overview | Internal peripheral resources]] that can be assigned to the master or the slave processor. | * [[STM32MP15 peripherals overview | Internal peripheral resources]] that can be assigned to the master or the slave processor. | ||
[[File:copro-hw-overview.png|link=]] | [[File:copro-hw-overview.png|900px|link=]] | ||
==Functional features and design== | ==Functional features and design== | ||
| Line 21: | Line 22: | ||
These frameworks are introduced in chapters below with links to dedicated articles for further explanation. | These frameworks are introduced in chapters below with links to dedicated articles for further explanation. | ||
[[File:copro-sw-overview.png| | [[File:copro-sw-overview.png|900px|link=]] | ||
===Load and control the Cortex-M firmware=== | ===Load and control the Cortex-M firmware=== | ||
The Linux OS integrates the[[Linux remoteproc framework overview | RemoteProc]] framework that allows to load firmware and control remote processors. | The Linux OS integrates the[[Linux remoteproc framework overview | RemoteProc]] framework that allows to load firmware and control remote processors. | ||
===Resources management (for shared peripheral, clocks, GPIOs...)=== | ===Resources management (for shared peripheral, clocks, GPIOs...)=== | ||
==== {{MicroprocessorDevice | device=15}} ==== | |||
The [[Resource_manager_for_coprocessing | resource manager]] proposes services to manage common resources and avoid any conflict. | The [[Resource_manager_for_coprocessing | resource manager]] proposes services to manage common resources and avoid any conflict. | ||
* '''Peripheral assignment request''': the mechanism used to ensure that a peripheral is reserved for a processor usage. The principle is that a firmware requests the peripheral before starting to use it, relying on the [[ETZPC_internal_peripheral| ETZPC]] table. | * '''Peripheral assignment request''': the mechanism used to ensure that a peripheral is reserved for a processor usage. The principle is that a firmware requests the peripheral before starting to use it, relying on the [[ETZPC_internal_peripheral| ETZPC]] table. | ||
:* On Cortex-A: At boot time, the ETZPC and Linux device tree are configured according to the [[TF-A_overview|TF-A]]<sup>®</sup> device tree (refer to [[How to assign an internal peripheral to | :* On Cortex-A: At boot time, the ETZPC and Linux device tree are configured according to the [[TF-A_overview|TF-A]]<sup>®</sup> device tree (refer to [[How to assign an internal peripheral to an execution context]] for details). | ||
:* On Cortex-M: the service is implemented by the '''Resource manager''' utilities. | :* On Cortex-M: the service is implemented by the '''Resource manager''' utilities. | ||
* '''Coprocessor resource configuration set''': services available in the main processor (Cortex-A running Linux) to configure the system resources needed to operate the peripheral on the coprocessor. The service is implemented by '''rproc_srm''' driver. | * '''Coprocessor resource configuration set''': services available in the main processor (Cortex-A running Linux) to configure the system resources needed to operate the peripheral on the coprocessor. The service is implemented by '''rproc_srm'''<ref name="rproc_srm_core.c">{{CodeSource | Linux kernel | drivers/remoteproc/rproc_srm_core.c| resource manager core driver rproc_srm_core.c}}</ref> <ref name="rproc_srm_dev.c">{{CodeSource | Linux kernel | drivers/remoteproc/rproc_srm_dev.c| resource manager device driver rproc_srm_dev.c}}</ref> drivers. | ||
==== {{MicroprocessorDevice | device=25}} ==== | |||
At boot time the [[Resource_Isolation_Framework_overview | resource isolation framework (RIF)]] configure the system to manage common resources and to assign/isolate/share peripherals. | |||
===Inter processor communication=== | ===Inter processor communication=== | ||
Inter processor communication is based on '''RPMsg''' framework and '''Mailbox''' mechanisms. | Inter processor communication is based on '''RPMsg''' framework and '''Mailbox''' mechanisms. | ||
[[File:copro-sw-ipc-overview.png| | [[File:copro-sw-ipc-overview.png|900px|link=]] | ||
*On Cortex-A: | *On Cortex-A: | ||
| Line 43: | Line 48: | ||
:* The RPMsg service is implemented by the [[Linux RPMsg framework overview| RPMsg]] framework. | :* The RPMsg service is implemented by the [[Linux RPMsg framework overview| RPMsg]] framework. | ||
:* The Mailbox service is implemented by the [[Linux Mailbox framework overview| stm32_ipcc mailbox ]] driver. | :* The Mailbox service is implemented by the [[Linux Mailbox framework overview| stm32_ipcc mailbox ]] driver. | ||
*On Cortex-M: | *On Cortex-M: | ||
:* The RPMsg service is implemented by the [https://www.openampproject.org OpenAMP] library . | :* The RPMsg service is implemented by the [https://www.openampproject.org OpenAMP] library. | ||
:* Some RPMsg virtual drivers (TTY, I2C,INTC,...) are implemented in the {{CodeSource | STM32CubeMP1 | Middlewares/Third_Party/OpenAMP/virtual_driver}}({{MicroprocessorDevice | device=15}}) and {{CodeSource | STM32CubeMP2 | Middlewares/Third_Party/OpenAMP/virtual_driver}}({{MicroprocessorDevice | device=25}}) | |||
:* The Mailbox service is implemented by the HAL_IPCC driver. | :* The Mailbox service is implemented by the HAL_IPCC driver. | ||
==References== | |||
<references /> | |||
<noinclude> | <noinclude> | ||
Latest revision as of 11:56, 12 June 2024
This article provides an overview of the management of the heterogeneous asymmetric architecture implemented in the STM32 MPU microprocessor family. It provides information on mechanisms put in place to help developers to design software in the multiprocessor system.
1. System overview
The STM32 MPU multiprocessor system allows to run independent firmwares on each CPU core. The below subsystems are involved in the management of the coexistence of the two CPU subsystems:
- An Arm® Cortex®-A acting as main processor and optimized to run the Linux® based OS.
- An Arm® Cortex®-M coprocessor which can run the RTOS optimized for microcontrollers or a bare-metal application.
- Internal memory regions with access granted for both the master and/or the slave processors:
- To load and execute coprocessor firmware and define static common structures.
- To share buffers for inter processing communication through a messaging infrastructure.
- An inter-processor communication controller peripheral allowing a signaling system by a dedicated mailbox.
- Internal peripheral resources that can be assigned to the master or the slave processor.
2. Functional features and design
In order to manage the coprocessor system, a list of services is proposed relying on the open-source RemoteProc and RPMsg frameworks. These frameworks are introduced in chapters below with links to dedicated articles for further explanation.
2.1. Load and control the Cortex-M firmware
The Linux OS integrates the RemoteProc framework that allows to load firmware and control remote processors.
2.2.1. STM32MP15x lines 
The resource manager proposes services to manage common resources and avoid any conflict.
- Peripheral assignment request: the mechanism used to ensure that a peripheral is reserved for a processor usage. The principle is that a firmware requests the peripheral before starting to use it, relying on the ETZPC table.
- On Cortex-A: At boot time, the ETZPC and Linux device tree are configured according to the TF-A® device tree (refer to How to assign an internal peripheral to an execution context for details).
- On Cortex-M: the service is implemented by the Resource manager utilities.
- Coprocessor resource configuration set: services available in the main processor (Cortex-A running Linux) to configure the system resources needed to operate the peripheral on the coprocessor. The service is implemented by rproc_srm[1] [2] drivers.
2.2.2. STM32MP25x lines
At boot time the resource isolation framework (RIF) configure the system to manage common resources and to assign/isolate/share peripherals.
2.3. Inter processor communication
Inter processor communication is based on RPMsg framework and Mailbox mechanisms.
- On Cortex-A:
- The RemoteProc framework is in charge of enabling the IPC on Linux side, based on information available in the firmware resource table.
- The RPMsg service is implemented by the RPMsg framework.
- The Mailbox service is implemented by the stm32_ipcc mailbox driver.
- On Cortex-M:
- The RPMsg service is implemented by the OpenAMP library.
- Some RPMsg virtual drivers (TTY, I2C,INTC,...) are implemented in the Middlewares/Third_Party/OpenAMP/virtual_driver (STM32MP15x lines ) and Middlewares/Third_Party/OpenAMP/virtual_driver (STM32MP25x lines )
- The Mailbox service is implemented by the HAL_IPCC driver.
3. References