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<noinclude>{{ApplicableFor | |||
|MPUs list=STM32MP13x, STM32MP15x, STM32MP25x | |||
|MPUs checklist=STM32MP13x, STM32MP15x, STM32MP25x | |||
}}</noinclude> | |||
==Article purpose== | ==Article purpose== | ||
The purpose of this article is to: | The purpose of this article is to: | ||
* | * Briefly introduce the STGEN peripheral and its main features. | ||
* | * Indicate the peripheral instance assignments at boot time and runtime (including whether instances can be allocated to secure contexts). | ||
* List the software frameworks and drivers managing the peripheral. | |||
* | * Explain how to configure the peripheral. | ||
==Peripheral overview== | ==Peripheral overview== | ||
The '''STGEN''' peripheral provides the reference clock used by the Arm<sup>®</sup> Cortex<sup>®</sup>-Axxx generic timer for its counters, including the system tick generation. | |||
It is clocked by either the HSI (High Speed Internal) oscillator or the HSE (High Speed External) oscillator. During the boot phase, STGEN is clocked by HSI until HSE is set up. This should be done at an early stage. Caution is needed when switching from one source to another, as the STGEN counter must be updated according to the new frequency. Otherwise, the time reference will be incorrect. | |||
The STGEN is a single-instance peripheral that can be accessed via the following two register sets: | |||
The STGEN is a single-instance peripheral that can be accessed via the two | * STGEN'''C''' for '''c'''ontrol: the '''secure''' port. | ||
* STGEN'''R''' for '''r'''ead-only access: the '''nonsecure''' port. | |||
Refer to the [[STM32 MPU resources#Reference manuals|STM32 MPU reference manuals]] for the complete list of features, and to the software frameworks and drivers, introduced in chapter 4 below, to see which features are implemented. | |||
On Arm 64-bit platforms, the update of the Arm CPU counter register can only be done by the highest exception level, which is TF-A BL31 on the {{MicroprocessorDevice | device=2}}. | |||
== | ==Peripheral usage== | ||
This chapter is applicable in the scope of '''OpenSTLinux BSP''' running on the Arm<sup>®</sup> Cortex<sup>®</sup>-A processors, and the '''STM32CubeMPU Package''' running on the Arm<sup>®</sup> Cortex<sup>®</sup>-M processor. | |||
==== | ===Boot time assignment=== | ||
====On {{MicroprocessorDevice | device=1}}==== | |||
The STGEN is first initialized by the [[STM32 MPU ROM code overview | ROM code]], then updated by the FSBL (see [[Boot chain overview]]) once the HSE clock is set up. | |||
{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp1_boottime}} | |||
<section begin=stm32mp13_boottime /><section begin=stm32mp15_boottime /> | |||
| rowspan="1" | Core | |||
| rowspan="1" | [[STGEN_internal_peripheral|STGEN]] | |||
| STGEN | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| | |||
| | |||
|- | |||
<section end=stm32mp13_boottime /><section end=stm32mp15_boottime /> | |||
|} | |||
==== | ====On {{MicroprocessorDevice | device=2}}==== | ||
{{: | {{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp2_a35_boottime}} | ||
| Core | <section begin=stm32mp25_a35_boottime /> | ||
| [[STGEN_internal_peripheral|STGEN]] | | rowspan="1" | Core | ||
| | | rowspan="1" | [[STGEN internal peripheral | STGEN]] | ||
| | | STGEN | ||
| | | <span title="system peripheral" style="font-size:21px">✓</span> | ||
| | | <span title="assigned peripheral" style="font-size:21px">☑</span> | ||
| <span style="font-size:14px">Read-only<br /><sup>(STGENR)</sup></span> | |||
| | |||
|- | |||
<section end=stm32mp25_a35_boottime /> | |||
|} | |||
===Runtime assignment=== | |||
====On {{MicroprocessorDevice | device=13}}==== | |||
{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp13_runtime}} | |||
<section begin=stm32mp13_runtime /> | |||
| rowspan="1" | Core | |||
| rowspan="1" | [[STGEN_internal_peripheral|STGEN]] | |||
| STGEN | |||
| <span title="system peripheral" style="font-size:21px">✓</span> | |||
| | |||
| | |||
|- | |- | ||
<section end=stm32mp13_runtime /> | |||
|} | |||
==== | ====On {{MicroprocessorDevice | device=15}}==== | ||
{{: | {{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp15_runtime}} | ||
< | <section begin=stm32mp15_runtime /> | ||
| rowspan="1" | Core | | rowspan="1" | Core | ||
| rowspan="1" | [[STGEN_internal_peripheral|STGEN]] | | rowspan="1" | [[STGEN_internal_peripheral|STGEN]] | ||
| STGEN | | STGEN | ||
| <span title="system peripheral" style="font-size:21px">✓</span> | | <span title="system peripheral" style="font-size:21px">✓</span> | ||
| | | | ||
| | | | ||
| | | | ||
|- | |- | ||
</ | <section end=stm32mp15_runtime /> | ||
|} | |||
====On {{MicroprocessorDevice | device=25}}==== | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp25_runtime}} | |||
<section begin=stm32mp25_a35_runtime /> | |||
| rowspan="1" | Core | |||
| rowspan="1" | [[STGEN internal peripheral | STGEN]] | |||
| STGEN | |||
| <span title="assigned peripheral" style="font-size:21px">☑</span><sup>OP-TEE</sup><br /><span title="assigned peripheral" style="font-size:21px">☑</span><sup>TF-A BL31</sup> | |||
| <span style="font-size:14px">Read-only<br /><sup>(STGENR)</sup></span> | |||
|<span style="font-size:14px">Read-only<br /><sup>(STGENR)</sup></span> | |||
|<span style="font-size:14px">Read-only<br /><sup>(STGENR)</sup></span> | |||
| | |||
| | |||
|- | |||
<section end=stm32mp25_a35_runtime /> | |||
|} | |||
==Software frameworks and drivers== | |||
Below are listed the software frameworks and drivers managing the STGEN peripheral for the embedded software components listed in the above tables. | |||
Linux<sup>®</sup>/U-Boot use the Arm<sup>®</sup> Cortex<sup>®</sup>-Axxx generic timer that gets its counter from the STGEN, but this is transparent at runtime. Therefore, there is no noticeable framework or driver for these components. | |||
==={{MicroprocessorDevice | device=1}}=== | |||
In OP-TEE, the STGEN's counter value is saved/restored during low-power sequences to keep platform time coherence. The STGEN configuration is done by TF-A. The frequency of the counter is restored in TF-A as well. | |||
==={{MicroprocessorDevice | device=25}}=== | |||
The STGEN configuration/restore is done by OP-TEE and the Arm counter frequency is set by TF-A BL31 upon receiving a specific SMC call from OP-TEE. | |||
===Sources=== | |||
* '''TF-A BL2''': {{CodeSource | TF-A | drivers/st/clk/stm32mp_clkfunc.c | STGEN configuration and frequency restoration }} | |||
* '''OP-TEE''': {{CodeSource | OP-TEE_OS | core/arch/arm/plat-stm32mp1/pm/context.c | Context saving }} | |||
* '''OP-TEE''': {{CodeSource | OP-TEE_OS | core/drivers/counter/stm32_stgen.c | STGEN driver }} ({{MicroprocessorDevice | device=25}}) | |||
==How to | ==How to assign and configure the peripheral== | ||
The peripheral assignment can be done via the [[STM32CubeMX]] graphical tool (and completed manually, if necessary).<br /> | |||
This tool can also be used to configure the peripheral: | |||
* Partial device tree (pin control and clock tree) generation for the OpenSTLinux software components. | |||
* HAL initialization code generation for the STM32CubeMPU Package. | |||
The configuration is applied by the firmware running in the context to which the peripheral is assigned. | |||
==References== | ==References== | ||
| Line 64: | Line 131: | ||
<noinclude> | <noinclude> | ||
[[Category:Core peripherals]] | [[Category:Core peripherals]] | ||
{{ArticleBasedOnModel| Internal peripheral article model}} | |||
{{PublicationRequestId | 28863 | 2023-10-24 | previous 8348 / PhilipS /2018-08-18 }} | |||
</noinclude> | </noinclude> | ||
Latest revision as of 10:37, 21 May 2024
1. Article purpose
The purpose of this article is to:
- Briefly introduce the STGEN peripheral and its main features.
- Indicate the peripheral instance assignments at boot time and runtime (including whether instances can be allocated to secure contexts).
- List the software frameworks and drivers managing the peripheral.
- Explain how to configure the peripheral.
2. Peripheral overview
The STGEN peripheral provides the reference clock used by the Arm® Cortex®-Axxx generic timer for its counters, including the system tick generation.
It is clocked by either the HSI (High Speed Internal) oscillator or the HSE (High Speed External) oscillator. During the boot phase, STGEN is clocked by HSI until HSE is set up. This should be done at an early stage. Caution is needed when switching from one source to another, as the STGEN counter must be updated according to the new frequency. Otherwise, the time reference will be incorrect.
The STGEN is a single-instance peripheral that can be accessed via the following two register sets:
- STGENC for control: the secure port.
- STGENR for read-only access: the nonsecure port.
Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced in chapter 4 below, to see which features are implemented.
On Arm 64-bit platforms, the update of the Arm CPU counter register can only be done by the highest exception level, which is TF-A BL31 on the STM32MP2 series.
3. Peripheral usage
This chapter is applicable in the scope of OpenSTLinux BSP running on the Arm® Cortex®-A processors, and the STM32CubeMPU Package running on the Arm® Cortex®-M processor.
3.1. Boot time assignment
3.1.1. On STM32MP1 series
The STGEN is first initialized by the ROM code, then updated by the FSBL (see Boot chain overview) once the HSE clock is set up.
Click on 
to expand or collapse the legend...
| Domain | Peripheral | Boot time allocation | Comment
| |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (ROM code) |
Cortex-A7 secure (TF-A BL2) |
Cortex-A7 non-secure (U-Boot) | |||
| Core | STGEN | STGEN | ✓ | ✓ | ||
3.1.2. On STM32MP2 series
Click on to expand or collapse the legend...
| Domain | Peripheral | Boot time allocation | Comment
| |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 non-secure (U-Boot) | |||
| Core | STGEN | STGEN | ✓ | ☑ | Read-only (STGENR) |
|
3.2. Runtime assignment
3.2.1. On STM32MP13x lines 
Click on to expand or collapse the legend...
| Domain | Peripheral | Runtime allocation | Comment
| ||
|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) | |||
| Core | STGEN | STGEN | ✓ | ||
3.2.2. On STM32MP15x lines
Click on to expand or collapse the legend...
| Domain | Peripheral | Runtime allocation | Comment
| |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) |
Cortex-M4 (STM32Cube) | |||
| Core | STGEN | STGEN | ✓ | |||
3.2.3. On STM32MP25x lines
Click on to expand or collapse the legend...
| Domain | Peripheral | Runtime allocation | Comment
| |||||
|---|---|---|---|---|---|---|---|---|
| Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 non-secure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 non-secure (STM32Cube) |
Cortex-M0+ (STM32Cube) | |||
| Core | STGEN | STGEN | ☑OP-TEE ☑TF-A BL31 |
Read-only (STGENR) |
Read-only (STGENR) |
Read-only (STGENR) |
||
4. Software frameworks and drivers
Below are listed the software frameworks and drivers managing the STGEN peripheral for the embedded software components listed in the above tables.
Linux®/U-Boot use the Arm® Cortex®-Axxx generic timer that gets its counter from the STGEN, but this is transparent at runtime. Therefore, there is no noticeable framework or driver for these components.
4.1. STM32MP1 series
In OP-TEE, the STGEN's counter value is saved/restored during low-power sequences to keep platform time coherence. The STGEN configuration is done by TF-A. The frequency of the counter is restored in TF-A as well.
4.2. STM32MP25x lines
The STGEN configuration/restore is done by OP-TEE and the Arm counter frequency is set by TF-A BL31 upon receiving a specific SMC call from OP-TEE.
4.3. Sources
- TF-A BL2: STGEN configuration and frequency restoration
- OP-TEE: Context saving
- OP-TEE: STGEN driver (STM32MP25x lines )
5. How to assign and configure the peripheral
The peripheral assignment can be done via the STM32CubeMX graphical tool (and completed manually, if necessary).
This tool can also be used to configure the peripheral:
- Partial device tree (pin control and clock tree) generation for the OpenSTLinux software components.
- HAL initialization code generation for the STM32CubeMPU Package.
The configuration is applied by the firmware running in the context to which the peripheral is assigned.
6. References