LPTIM internal peripheral

Applicable for

STM32MP13x lines, STM32MP15x lines, Unknown MPU

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1. Article purpose

The purpose of this article is to:

• briefly introduce the LPTIM peripheral and its main features,
• indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
• list the software frameworks and drivers managing the peripheral,
• explain how to configure the peripheral.

2. Peripheral overview

The LPTIM peripheral is a single channel low-power timer unit, that can continue to run even during low power modes when it selects a clock source that remains active in RCC.

The LPTIM peripheral is available in different configurations. Depending on the selected instance, it can act as PWM, quadrature encoder, external event counter or trigger source for other internal peripherals, like ADC, DAC and DFSDM (on STM32MP1 Series) or MDF (on STM32MP2 unknown microprocessor device).

• LPTIM on STM32MP1 Series

LPTIM features	PWM	External event counter Trigger source	Quadrature encoder
LPTIM1, LPTIM2
LPTIM3
LPTIM4, LPTIM5

• LPTIM on STM32MP2 unknown microprocessor device

LPTIM features	PWM	External event counter Trigger source	Quadrature encoder
LPTIM1, LPTIM2
LPTIM3, LPTIM4, LPTIM5

• On STM32MP13x lines , LPTIM3 can be used for RCC HSE clock source monitoring
• On STM32MP25 unknown microprocessor device, LPTIM can have up to 2 independent channels. It also supports input capture. LPTIM1 can be used for RCC HSE monitoring.

Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.

3. Peripheral usage

This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm^® Cortex^®-A processor(s), and the STM32CubeMPU Package running on the Arm^® Cortex^®-M processor.

3.1. Boot time assignment

3.1.1. On STM32MP13x lines 

Expand

Click on the right to expand the legend...

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

• ☐ means that the peripheral can be assigned (☑) to the given boot time context.
• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
• ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
		Instance	Cortex-A7 secure (ROM code)	Cortex-A7 secure (TF-A BL2)	Cortex-A7 non-secure (U-Boot)
Core/Timers	LPTIM	LPTIM1			⬚
		LPTIM2		⬚	⬚
		LPTIM3		⬚	⬚
		LPTIM4			⬚
		LPTIM5			⬚

3.1.2. On STM32MP15x lines 

Expand

Click on the right to expand the legend...

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

• ☐ means that the peripheral can be assigned (☑) to the given boot time context.
• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
• ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
		Instance	Cortex-A7 secure (ROM code)	Cortex-A7 secure (TF-A BL2)	Cortex-A7 non-secure (U-Boot)
Core/Timers	LPTIM	LPTIMx (x = 1 to 5)		⬚	⬚	LPTIM are not used at boot time.

3.1.3. On STM32MP25 unknown microprocessor device

Click on to expand or collapse the legend...

• ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
• ☐ means that the peripheral can be assigned to the given boot time context.
• ☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.

Domain	Peripheral	Boot time allocation				Comment
		Instance	Cortex-A35 secure (ROM code)	Cortex-A35 secure (TF-A BL2)	Cortex-A35 non-secure (U-Boot)
Core/Timers	LPTIM	LPTIMx (x = 1 to 5)		⬚	⬚	LPTIM are not used at boot time.

3.2. Runtime assignment

3.2.1. On STM32MP13x lines 

Expand

Click on the right to expand the legend...

STM32MP13 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

• ☐ means that the peripheral can be assigned (☑) to the given runtime context.
• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
• ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP13 reference manuals.

Domain	Peripheral	Runtime allocation			Comment
		Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)
Core/Timers	LPTIM	LPTIM1		☐
		LPTIM2	☐	☐	Assignment (single choice)
		LPTIM3	☐	☐	Assignment (single choice) LPTIM3 can be used for HSE monitoring
		LPTIM4		☐
		LPTIM5		☐

3.2.2. On STM32MP15x lines 

Expand

Click on the right to expand the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

• ☐ means that the peripheral can be assigned (☑) to the given runtime context.
• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
• ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain	Peripheral	Runtime allocation				Comment
		Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Cortex-M4 (STM32Cube)
Core/Timers	LPTIM	LPTIMx (x = 1 to 5)		☐	☐	Assignment (single choice)

3.2.3. On STM32MP25 unknown microprocessor device

Click on to expand or collapse the legend...

STM32MP25 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
• ☐ means that the peripheral can be assigned to the given runtime context.
• ☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
• ✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP25 reference manuals.

Domain	Peripheral	Runtime allocation						Comment
		Instance	Cortex-A35 secure (OP-TEE / TF-A BL31)	Cortex-A35 non-secure (Linux)	Cortex-M33 secure (TF-M)	Cortex-M33 non-secure (STM32Cube)	Cortex-M0+ (STM32Cube)
Core/Timers	LPTIM	LPTIM1	☐OP-TEE	☐	⬚	☐		LPTIM1 can be used for HSE monitoring.
		LPTIM2	☐OP-TEE	☐	⬚	☐
		LPTIM3	☐OP-TEE	☐	⬚	☐	☐
		LPTIM4	☐OP-TEE	☐	⬚	☐	☐
		LPTIM5	☐OP-TEE	☐	⬚	☐	☐

4. Software frameworks and drivers

Below are listed the software frameworks and drivers managing the LPTIM peripheral for the embedded software components listed in the above tables.

• Linux^®: PWM framework, IIO framework, Counter framework, and Clock events framework
• OP-TEE: OP-TEE LPTIM driver
• STM32Cube: HAL LPTIM driver

5. How to assign and configure the peripheral

The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:

• partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
• HAL initialization code generation for the STM32CubeMPU Package.

The configuration is applied by the firmware running in the context in which the peripheral is assigned.

For Linux kernel configuration, please refer to LPTIM device tree configuration and STM32 LPTIM Linux driver articles.