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<noinclude>{{ApplicableFor | |||
|MPUs list=STM32MP13x, STM32MP15x, STM32MP25x | |||
|MPUs checklist=STM32MP13x,STM32MP15x, STM32MP25x | |||
}}</noinclude> | |||
==Article purpose== | ==Article purpose== | ||
The purpose of this article is to | The purpose of this article is to: | ||
* briefly introduce the | * briefly introduce the LPTIM peripheral and its main features, | ||
* indicate the | * indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts), | ||
* list the software frameworks and drivers managing the peripheral, | |||
* explain how to configure the | * explain how to configure the peripheral. | ||
==Peripheral overview== | ==Peripheral overview== | ||
The '''LPTIM''' peripheral is a single channel low-power timer unit, that can continue to run even during [[Power overview|low power modes]] when it selects a clock source that remains active in [[RCC internal peripheral|RCC]]. | The '''LPTIM''' peripheral is a single channel low-power timer unit, that can continue to run even during [[Power overview|low power modes]] when it selects a clock source that remains active in [[RCC internal peripheral|RCC]]. | ||
=== | The LPTIM peripheral is available in different configurations. Depending on the selected instance, it can act as PWM, quadrature encoder<ref name="quadrature_encoder">[https://en.wikipedia.org/wiki/Rotary_encoder#Incremental_rotary_encoder Quadrature encoder]</ref>, | ||
Refer to [[ | external event counter or trigger source for other internal peripherals, like [[ADC internal peripheral|ADC]], [[DAC internal peripheral|DAC]] and [[DFSDM internal peripheral|DFSDM]] (on {{MicroprocessorDevice | device=1}}) or [[MDF internal peripheral|MDF]] (on {{MicroprocessorDevice | device=2}}). | ||
* LPTIM on {{MicroprocessorDevice | device=1}} | |||
{| class="st-table" style="width: 100%;" | |||
|- style="background: {{STLightGrey}};" | |||
! style="width:40%; | LPTIM features | |||
! style="width:20%; | PWM | |||
! style="width:20%;" | External event counter <br/>Trigger source | |||
! style="width:20%;" | Quadrature encoder | |||
|- | |||
| LPTIM1, LPTIM2 | |||
| {{Y}} | |||
| {{Y}} | |||
| {{Y}} | |||
|- | |||
| LPTIM3 | |||
| {{Y}} | |||
| {{Y}} | |||
| | |||
|- | |||
| LPTIM4, LPTIM5 | |||
| {{Y}} | |||
| | |||
| | |||
|- | |||
|} | |||
* LPTIM on {{MicroprocessorDevice | device=2}} | |||
{| class="st-table" style="width: 100%;" | |||
|- style="background: {{STLightGrey}};" | |||
! style="width:40%; | LPTIM features | |||
! style="width:20%; | PWM | |||
! style="width:20%;" | External event counter <br/>Trigger source | |||
! style="width:20%;" | Quadrature encoder | |||
|- | |||
| LPTIM1, LPTIM2 | |||
| {{Y}} | |||
| {{Y}} | |||
| {{Y}} | |||
|- | |||
| LPTIM3, LPTIM4, LPTIM5 | |||
| {{Y}} | |||
| {{Y}} | |||
| | |||
|- | |||
|} | |||
* On {{MicroprocessorDevice | device=13}}, LPTIM3 can be used for [[RCC internal peripheral|RCC]] HSE clock source monitoring | |||
* On {{MicroprocessorDevice | device=25}}, LPTIM can have up to 2 independent channels. It also supports input capture. LPTIM1 can be used for [[RCC internal peripheral|RCC]] HSE monitoring. | |||
Refer to the [[STM32 MPU resources#Reference manuals|STM32 MPU reference manuals]] for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented. | |||
==Peripheral usage== | |||
This chapter is applicable in the scope of the '''OpenSTLinux BSP''' running on the Arm<sup>®</sup> Cortex<sup>®</sup>-A processor(s), and the '''STM32CubeMPU Package''' running on the Arm<sup>®</sup> Cortex<sup>®</sup>-M processor. | |||
===Boot time assignment=== | |||
====On {{MicroprocessorDevice | device=13}}==== | |||
{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp1_boottime}} | |||
<section begin=stm32mp13_boottime /> | |||
| rowspan="5" | Core/Timers | |||
| rowspan="5" | [[LPTIM internal peripheral | LPTIM]] | |||
| LPTIM1 | |||
| | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| LPTIM2 | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| LPTIM3 | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| LPTIM4 | |||
| | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
| LPTIM5 | |||
| | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| | |||
|- | |||
<section end=stm32mp13_boottime /> | |||
|} | |||
====On {{MicroprocessorDevice | device=15}}==== | |||
{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp1_boottime}} | |||
<section begin=stm32mp15_boottime /> | |||
| rowspan="1" | Core/Timers | |||
| rowspan="1" | [[LPTIM internal peripheral | LPTIM]] | |||
| LPTIMx (x = 1 to 5) | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| LPTIM are not used at boot time. | |||
|- | |||
<section end=stm32mp15_boottime /> | |||
|} | |||
====On {{MicroprocessorDevice | device=25}}==== | |||
{{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp2_a35_boottime}} | |||
<section begin=stm32mp25_a35_boottime /> | |||
| rowspan="1" | Core/Timers | |||
| rowspan="1" | [[LPTIM internal peripheral | LPTIM]] | |||
| LPTIMx (x = 1 to 5) | |||
| | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| LPTIM are not used at boot time. | |||
|- | |||
<section end=stm32mp25_a35_boottime /> | |||
|} | |||
=== | ===Runtime assignment=== | ||
====On {{MicroprocessorDevice | device=13}}==== | |||
{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp13_runtime}} | |||
<section begin=stm32mp13_runtime /> | |||
| rowspan="5" | Core/Timers | |||
| rowspan="5" | [[LPTIM internal peripheral|LPTIM]] | |||
| LPTIM1 | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| LPTIM2 | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| Assignment (single choice) | |||
|- | |||
| LPTIM3 | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| Assignment (single choice)<br>LPTIM3 can be used for HSE monitoring | |||
|- | |||
| LPTIM4 | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| LPTIM5 | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
<section end=stm32mp13_runtime /> | |||
|} | |||
== | ====On {{MicroprocessorDevice | device=15}}==== | ||
=== | {{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp15_runtime}} | ||
<section begin=stm32mp15_runtime /> | |||
| rowspan="1" | Core/Timers | |||
| rowspan="1" | [[LPTIM internal peripheral|LPTIM]] | |||
| LPTIMx (x = 1 to 5) | |||
| | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| Assignment (single choice) | |||
|- | |||
<section end=stm32mp15_runtime /> | |||
|} | |||
=== | ====On {{MicroprocessorDevice | device=25}}==== | ||
==== | {{#lst:STM32MP2_internal_peripherals_assignment_table_template|stm32mp25_runtime}} | ||
<section begin=stm32mp25_a35_runtime /> | |||
| rowspan="5" | Core/Timers | |||
| rowspan="5" | [[LPTIM internal peripheral | LPTIM]] | |||
| LPTIM1 | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| LPTIM1 can be used for HSE monitoring. | |||
|- | |||
| LPTIM2 | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
| | |||
|- | |||
| LPTIM3 | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| LPTIM4 | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
| LPTIM5 | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span><sup>OP-TEE</sup> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | |||
| | |||
|- | |||
<section end=stm32mp25_a35_runtime /> | |||
|} | |||
==Software frameworks and drivers== | |||
Below are listed the software frameworks and drivers managing the LPTIM peripheral for the embedded software components listed in the above tables. | |||
== | * '''Linux<sup>®</sup>''': [[PWM overview|PWM framework]], [[IIO overview|IIO framework]], ''Counter'' framework, and ''Clock events'' framework | ||
The | * '''OP-TEE''': {{CodeSource | OP-TEE_OS | core/drivers/counter/stm32_lptimer.c |OP-TEE LPTIM driver}} | ||
* '''STM32Cube''': {{CodeSource | STM32CubeMP1 | Drivers/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_lptim.c | HAL LPTIM driver}} | |||
==How to assign and configure the peripheral== | |||
The peripheral assignment can be done via the [[STM32CubeMX]] graphical tool (and manually completed if needed).<br /> | |||
This tool also helps to configure the peripheral: | |||
* partial device trees (pin control and clock tree) generation for the OpenSTLinux software components, | |||
* HAL initialization code generation for the STM32CubeMPU Package. | |||
The configuration is applied by the firmware running in the context in which the peripheral is assigned. | |||
For Linux kernel configuration, please refer to [[LPTIM device tree configuration]] and [[LPTIM Linux driver|STM32 LPTIM Linux driver]] articles. | For Linux kernel configuration, please refer to [[LPTIM device tree configuration]] and [[LPTIM Linux driver|STM32 LPTIM Linux driver]] articles. | ||
==References== | ==References== | ||
Line 90: | Line 256: | ||
<noinclude> | <noinclude> | ||
[[Category:Timers peripherals]] | [[Category:Timers peripherals]] | ||
{{ArticleBasedOnModel | Internal peripheral article model}} | |||
{{PublicationRequestId | 7894 | 2018-07-03 | AlainF}} | {{PublicationRequestId | 7894 | 2018-07-03 | AlainF}} | ||
</noinclude> | </noinclude> |
Latest revision as of 18:00, 13 May 2024
1. Article purpose
The purpose of this article is to:
- briefly introduce the LPTIM peripheral and its main features,
- indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
- list the software frameworks and drivers managing the peripheral,
- explain how to configure the peripheral.
2. Peripheral overview
The LPTIM peripheral is a single channel low-power timer unit, that can continue to run even during low power modes when it selects a clock source that remains active in RCC.
The LPTIM peripheral is available in different configurations. Depending on the selected instance, it can act as PWM, quadrature encoder[1], external event counter or trigger source for other internal peripherals, like ADC, DAC and DFSDM (on STM32MP1 series) or MDF (on STM32MP2 series).
- LPTIM on STM32MP1 series
LPTIM features | PWM | External event counter Trigger source |
Quadrature encoder |
---|---|---|---|
LPTIM1, LPTIM2 | ![]() |
![]() |
![]() |
LPTIM3 | ![]() |
![]() |
|
LPTIM4, LPTIM5 | ![]() |
- LPTIM on STM32MP2 series
LPTIM features | PWM | External event counter Trigger source |
Quadrature encoder |
---|---|---|---|
LPTIM1, LPTIM2 | ![]() |
![]() |
![]() |
LPTIM3, LPTIM4, LPTIM5 | ![]() |
![]() |
- On STM32MP13x lines
, LPTIM3 can be used for RCC HSE clock source monitoring
- On STM32MP25x lines
, LPTIM can have up to 2 independent channels. It also supports input capture. LPTIM1 can be used for RCC HSE monitoring.
Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.
3. Peripheral usage
This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm® Cortex®-A processor(s), and the STM32CubeMPU Package running on the Arm® Cortex®-M processor.
3.1. Boot time assignment
3.1.1. On STM32MP13x lines 
Click on to expand or collapse the legend...
Domain | Peripheral | Boot time allocation | Comment ![]() | |||
---|---|---|---|---|---|---|
Instance | Cortex-A7 secure (ROM code) |
Cortex-A7 secure (TF-A BL2) |
Cortex-A7 non-secure (U-Boot) | |||
Core/Timers | LPTIM | LPTIM1 | ⬚ | |||
LPTIM2 | ⬚ | ⬚ | ||||
LPTIM3 | ⬚ | ⬚ | ||||
LPTIM4 | ⬚ | |||||
LPTIM5 | ⬚ |
3.1.2. On STM32MP15x lines 
Click on to expand or collapse the legend...
Domain | Peripheral | Boot time allocation | Comment ![]() | |||
---|---|---|---|---|---|---|
Instance | Cortex-A7 secure (ROM code) |
Cortex-A7 secure (TF-A BL2) |
Cortex-A7 non-secure (U-Boot) | |||
Core/Timers | LPTIM | LPTIMx (x = 1 to 5) | ⬚ | ⬚ | LPTIM are not used at boot time. |
3.1.3. On STM32MP25x lines 
Click on to expand or collapse the legend...
Domain | Peripheral | Boot time allocation | Comment ![]() | |||
---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (ROM code) |
Cortex-A35 secure (TF-A BL2) |
Cortex-A35 non-secure (U-Boot) | |||
Core/Timers | LPTIM | LPTIMx (x = 1 to 5) | ⬚ | ⬚ | LPTIM are not used at boot time. |
3.2. Runtime assignment
3.2.1. On STM32MP13x lines 
Click on to expand or collapse the legend...
Domain | Peripheral | Runtime allocation | Comment ![]() | ||
---|---|---|---|---|---|
Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) | |||
Core/Timers | LPTIM | LPTIM1 | ☐ | ||
LPTIM2 | ☐ | ☐ | Assignment (single choice) | ||
LPTIM3 | ☐ | ☐ | Assignment (single choice) LPTIM3 can be used for HSE monitoring | ||
LPTIM4 | ☐ | ||||
LPTIM5 | ☐ |
3.2.2. On STM32MP15x lines 
Click on to expand or collapse the legend...
Domain | Peripheral | Runtime allocation | Comment ![]() | |||
---|---|---|---|---|---|---|
Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) |
Cortex-M4 (STM32Cube) | |||
Core/Timers | LPTIM | LPTIMx (x = 1 to 5) | ☐ | ☐ | Assignment (single choice) |
3.2.3. On STM32MP25x lines 
Click on to expand or collapse the legend...
Domain | Peripheral | Runtime allocation | Comment ![]() | |||||
---|---|---|---|---|---|---|---|---|
Instance | Cortex-A35 secure (OP-TEE / TF-A BL31) |
Cortex-A35 non-secure (Linux) |
Cortex-M33 secure (TF-M) |
Cortex-M33 non-secure (STM32Cube) |
Cortex-M0+![]() (STM32Cube) | |||
Core/Timers | LPTIM | LPTIM1 | ☐OP-TEE | ☐ | ⬚ | ☐ | LPTIM1 can be used for HSE monitoring. | |
LPTIM2 | ☐OP-TEE | ☐ | ⬚ | ☐ | ||||
LPTIM3 | ☐OP-TEE | ☐ | ⬚ | ☐ | ☐ | |||
LPTIM4 | ☐OP-TEE | ☐ | ⬚ | ☐ | ☐ | |||
LPTIM5 | ☐OP-TEE | ☐ | ⬚ | ☐ | ☐ |
4. Software frameworks and drivers
Below are listed the software frameworks and drivers managing the LPTIM peripheral for the embedded software components listed in the above tables.
- Linux®: PWM framework, IIO framework, Counter framework, and Clock events framework
- OP-TEE: OP-TEE LPTIM driver
- STM32Cube: HAL LPTIM driver
5. How to assign and configure the peripheral
The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:
- partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
- HAL initialization code generation for the STM32CubeMPU Package.
The configuration is applied by the firmware running in the context in which the peripheral is assigned.
For Linux kernel configuration, please refer to LPTIM device tree configuration and STM32 LPTIM Linux driver articles.
6. References