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<noinclude>{{ApplicableFor | <noinclude>{{ApplicableFor | ||
|MPUs list=STM32MP13x, STM32MP15x | |MPUs list=STM32MP13x, STM32MP15x | ||
|MPUs checklist=STM32MP13x,STM32MP15x | |MPUs checklist=STM32MP13x,STM32MP15x, STM32MP25x | ||
}}</noinclude> | }}</noinclude> | ||
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| rowspan="1" | [[QUADSPI internal peripheral|QUADSPI]] | | rowspan="1" | [[QUADSPI internal peripheral|QUADSPI]] | ||
| QUADSPI | | QUADSPI | ||
| <span title=" | | <span title="system peripheral" style="font-size:21px">✓</span> | ||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | | <span title="assignable peripheral" style="font-size:21px">☐</span> | ||
| <span title="assignable peripheral" style="font-size:21px">☐</span> | | <span title="assignable peripheral" style="font-size:21px">☐</span> | ||
| Line 70: | Line 70: | ||
Below are listed the software frameworks and drivers managing the QUADSPI peripheral for the embedded software components listed in the above tables. | Below are listed the software frameworks and drivers managing the QUADSPI peripheral for the embedded software components listed in the above tables. | ||
* '''Linux<sup>®</sup>''': [[MTD overview|MTD framework]] and driver ({{CodeSource | Linux kernel | drivers/spi/spi-stm32.c}}) | * '''Linux<sup>®</sup>''': [[MTD overview|MTD framework]] and driver ({{CodeSource | Linux kernel | drivers/spi/spi-stm32-qspi.c}}) | ||
* '''STM32Cube''': [[ | * '''STM32Cube''': [[STM32CubeMP15 Package architecture|QUADSPI HAL driver]] and {{CodeSource | STM32CubeMP1 | Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_qspi.h | header file of QUADSPI HAL module}} | ||
* '''TF-A BL2''': MTD frameworks ({{CodeSource | TF-A | drivers/mtd/}}) and driver ({{CodeSource | TF-A | drivers/st/spi/stm32_qspi.c}}) | * '''TF-A BL2''': MTD frameworks ({{CodeSource | TF-A | drivers/mtd/}}) and driver ({{CodeSource | TF-A | drivers/st/spi/stm32_qspi.c}}) | ||
* '''U-Boot''': MTD frameworks ({{CodeSource | U-Boot | drivers/mtd/}}) and drivers ({{CodeSource | U-Boot | drivers/spi/stm32_qspi.c}}) | * '''U-Boot''': MTD frameworks ({{CodeSource | U-Boot | drivers/mtd/}}) and drivers ({{CodeSource | U-Boot | drivers/spi/stm32_qspi.c}}) | ||
Latest revision as of 14:53, 4 January 2024
1. Article purpose
The purpose of this article is to:
- briefly introduce the QUADSPI peripheral and its main features,
- indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
- list the software frameworks and drivers managing the peripheral,
- explain how to configure the peripheral.
2. Peripheral overview
The QUADSPI peripheral interfaces the processor with serial NOR flash and serial NAND flash memories.
It supports:
- Single, Dual- or Quad-SPI flash memories
- A dual-flash mode, allowing to aggregate two flash memories into a virtual-single one
- Dual data rate and memory-mapped modes.
Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.
3. Peripheral usage
This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm® Cortex®-A processor(s), and the STM32CubeMPU Package running on the Arm® Cortex®-M processor.
3.1. Boot time assignment
3.1.1. On STM32MP1 Series
QUADSPI instance is a boot device that supports serial boot for flash programming with STM32CubeProgrammer.
Click on the right to expand the legend...
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ☐ means that the peripheral can be assigned (☑) to the given boot time context.
- ⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.
| Domain | Peripheral | Boot time allocation | Comment | |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (ROM code) |
Cortex-A7 secure (TF-A BL2) |
Cortex-A7 non-secure (U-Boot) | |||
| Mass storage | QUADSPI | QUADSPI | ✓ | ☐ | ☐ | |
3.2. Runtime assignment
3.2.1. On STM32MP13x lines 
Click on the right to expand the legend...
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ☐ means that the peripheral can be assigned (☑) to the given runtime context.
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.
Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP13 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment | ||
|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) | |||
| Mass storage | QUADSPI | QUADSPI | ⬚ | ☐ | Assignment (single choice) |
3.2.2. On STM32MP15x lines
Click on the right to expand the legend...
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ☐ means that the peripheral can be assigned (☑) to the given runtime context.
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.
Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment | |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) |
Cortex-M4 (STM32Cube) | |||
| Mass storage | QUADSPI | QUADSPI | ☐ | ☐ | Assignment (single choice) | |
4. Software frameworks and drivers
Below are listed the software frameworks and drivers managing the QUADSPI peripheral for the embedded software components listed in the above tables.
- Linux®: MTD framework and driver (drivers/spi/spi-stm32-qspi.c )
- STM32Cube: QUADSPI HAL driver and header file of QUADSPI HAL module
- TF-A BL2: MTD frameworks (drivers/mtd/ ) and driver (drivers/st/spi/stm32_qspi.c )
- U-Boot: MTD frameworks (drivers/mtd/ ) and drivers (drivers/spi/stm32_qspi.c )
5. How to assign and configure the peripheral
The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:
- partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
- HAL initialization code generation for the STM32CubeMPU Package.
The configuration is applied by the firmware running in the context in which the peripheral is assigned.
For Linux kernel configuration, refer to QUADSPI device tree configuration.