QUADSPI internal peripheral: Difference between revisions

VisualWikitext

Latest revision as of 14:53, 4 January 2024

Applicable for

STM32MP13x lines, STM32MP15x lines

1. Article purpose

The purpose of this article is to:

briefly introduce the QUADSPI peripheral and its main features,
indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
list the software frameworks and drivers managing the peripheral,
explain how to configure the peripheral.

2. Peripheral overview

The QUADSPI peripheral interfaces the processor with serial NOR flash and serial NAND flash memories.
It supports:

Single, Dual- or Quad-SPI flash memories
A dual-flash mode, allowing to aggregate two flash memories into a virtual-single one
Dual data rate and memory-mapped modes.

Refer to the STM32 MPU reference manuals for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.

3. Peripheral usage

This chapter is applicable in the scope of the OpenSTLinux BSP running on the Arm^® Cortex^®-A processor(s), and the STM32CubeMPU Package running on the Arm^® Cortex^®-M processor.

3.1. Boot time assignment

3.1.1. On STM32MP1 Series

QUADSPI instance is a boot device that supports serial boot for flash programming with STM32CubeProgrammer.

Click on to expand or collapse the legend...

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

⬚ means that the peripheral can be assigned to the given boot time context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
☐ means that the peripheral can be assigned to the given boot time context.
☑ means that the peripheral is assigned by default to the given boot time context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32 MPU reference manuals.

Domain	Peripheral	Boot time allocation				Comment
Domain	Peripheral	Instance	Cortex-A7 secure (ROM code)	Cortex-A7 secure (TF-A BL2)	Cortex-A7 non-secure (U-Boot)	Comment
Mass storage	QUADSPI	QUADSPI	✓	☐	☐

3.2. Runtime assignment

3.2.1. On STM32MP13x lines

Click on to expand or collapse the legend...

STM32MP13 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
☐ means that the peripheral can be assigned to the given runtime context.
☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possibilities might be described in STM32MP13 reference manuals.

Domain	Peripheral	Runtime allocation			Comment
Domain	Peripheral	Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Comment
Mass storage	QUADSPI	QUADSPI	⬚	☐	Assignment (single choice)

3.2.2. On STM32MP15x lines

Click on to expand or collapse the legend...

STM32MP15 internal peripherals

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
☐ means that the peripheral can be assigned to the given runtime context.
☑ means that the peripheral is assigned by default to the given runtime context and that the peripheral is mandatory for the STM32 MPU Embedded Software distribution.
✓ is used for system peripherals that cannot be unchecked because they are hardware connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.

Domain	Peripheral	Runtime allocation				Comment
Domain	Peripheral	Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)	Cortex-M4 (STM32Cube)	Comment
Mass storage	QUADSPI	QUADSPI		☐	☐	Assignment (single choice)

4. Software frameworks and drivers

Below are listed the software frameworks and drivers managing the QUADSPI peripheral for the embedded software components listed in the above tables.

Linux^®: MTD framework and driver (drivers/spi/spi-stm32-qspi.c )
STM32Cube: QUADSPI HAL driver and header file of QUADSPI HAL module
TF-A BL2: MTD frameworks (drivers/mtd/ ) and driver (drivers/st/spi/stm32_qspi.c )
U-Boot: MTD frameworks (drivers/mtd/ ) and drivers (drivers/spi/stm32_qspi.c )

5. How to assign and configure the peripheral

The peripheral assignment can be done via the STM32CubeMX graphical tool (and manually completed if needed).
This tool also helps to configure the peripheral:

partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
HAL initialization code generation for the STM32CubeMPU Package.

The configuration is applied by the firmware running in the context in which the peripheral is assigned.

For Linux kernel configuration, refer to QUADSPI device tree configuration.

@@ Line 1: / Line 1: @@
 <noinclude>{{ApplicableFor
 |MPUs list=STM32MP13x, STM32MP15x
-|MPUs checklist=STM32MP13x,STM32MP15x
+|MPUs checklist=STM32MP13x,STM32MP15x, STM32MP25x
 }}</noinclude>
 ==Article purpose==
-The purpose of this article is to
+The purpose of this article is to:
-* briefly introduce the QUADSPI peripheral and its main features
+* briefly introduce the QUADSPI peripheral and its main features,
-* indicate the level of security supported by this hardware block
+* indicate the peripheral instances assignment at boot time and their assignment at runtime (including whether instances can be allocated to secure contexts),
-* explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
+* list the software frameworks and drivers managing the peripheral,
-* explain, when needed, how to configure the QUADSPI peripheral.
+* explain how to configure the peripheral.
 ==Peripheral overview==
-The Quad-SPI interface ('''QUADSPI''' peripheral) interfaces the processor with serial NOR flash and serial NAND flash memories. <br />
+The '''QUADSPI''' peripheral interfaces the processor with serial NOR flash and serial NAND flash memories. <br />
 It supports:
 * Single, Dual- or Quad-SPI flash memories
@@ Line 18: / Line 18: @@
 * Dual data rate and memory-mapped modes.
-===Features===
+Refer to the [[STM32 MPU resources#Reference manuals|STM32 MPU reference manuals]] for the complete list of features, and to the software frameworks and drivers, introduced below, to see which features are implemented.
-Refer to [[STM32MP13 resources#Reference manuals|STM32MP13 reference manuals]] or [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete feature list and to the software components introduced below to know the implemented features.
-===Security support===
+==Peripheral usage==
-==== On {{MicroprocessorDevice | device=13}} ====
+This chapter is applicable in the scope of the '''OpenSTLinux BSP''' running on the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A processor(s), and the '''STM32CubeMPU Package''' running on the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M processor.
-The QUADSPI  is a '''secure''' peripheral (under [[ETZPC_internal_peripheral|ETZPC]] control).
-==== On {{MicroprocessorDevice | device=15}} ====
-The QUADSPI is a '''non-secure''' peripheral.
-==Using the peripheral-associated software==
+===Boot time assignment===
-===Boot time===
+====On {{MicroprocessorDevice | device=1}}====
 QUADSPI instance is a boot device that supports serial boot for flash programming with [[STM32CubeProgrammer]].
+{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp1_boottime}}
+<section begin=stm32mp13_boottime /><section begin=stm32mp15_boottime />
+| rowspan="1" | Mass storage
+| rowspan="1" | [[QUADSPI internal peripheral|QUADSPI]]
+| QUADSPI
+| <span title="system peripheral" style="font-size:21px">✓</span>
+| <span title="assignable peripheral" style="font-size:21px">☐</span>
+| <span title="assignable peripheral" style="font-size:21px">☐</span>
+|
+|-
+<section end=stm32mp13_boottime /><section end=stm32mp15_boottime />
+|}
-===Runtime===
+===Runtime assignment===
-====Overview====
+====On {{MicroprocessorDevice | device=13}}====
-Allocation of the QUADSPI instances can be:
+{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp13_runtime}}
-* The Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure context, on {{MicroprocessorDevice | device=13}} only, but this is not supported in OpenSTLinux.
+<section begin=stm32mp13_runtime />
-or
+| rowspan="1" | Mass storage
-* The Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure core to be controlled in Linux<sup>&reg;</sup> by the [[MTD overview|MTD]] framework
+| rowspan="1" | [[QUADSPI internal peripheral|QUADSPI]]
-or
+| QUADSPI
-* The Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4, on {{MicroprocessorDevice | device=15}} only, to be controlled in STM32Cube MPU Package by [[STM32CubeMP1 architecture|QUADSPI HAL driver]]
+| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span>
+| <span title="assignable peripheral" style="font-size:21px">☐</span>
+| Assignment (single choice)
+|-
+<section end=stm32mp13_runtime />
+|}
-Chapter [[#Peripherals assignment]] describes which peripheral instances can be assigned to which context.
+====On {{MicroprocessorDevice | device=15}}====
+{{#lst:STM32MP1_internal_peripherals_assignment_table_template|stm32mp15_runtime}}
+<section begin=stm32mp15_runtime />
+| rowspan="1" | Mass storage
+| rowspan="1" | [[QUADSPI internal peripheral|QUADSPI]]
+| QUADSPI
+|
+| <span title="assignable peripheral" style="font-size:21px">☐</span>
+| <span title="assignable peripheral" style="font-size:21px">☐</span>
+| Assignment (single choice)
+|-
+<section end=stm32mp15_runtime />
+|}
-====Software frameworks====
+==Software frameworks and drivers==
-===== On {{MicroprocessorDevice | device=13}} =====
+Below are listed the software frameworks and drivers managing the QUADSPI peripheral for the embedded software components listed in the above tables.
-{{: STM32MP13 internal peripherals software table template}}
- | Mass storage
- | [[QUADSPI internal peripheral|QUADSPI]]
- |
- | [[MTD overview|Linux MTD framework]]
- |
- |-
- |}
-===== On {{MicroprocessorDevice | device=15}} =====
-{{:STM32MP15_internal_peripherals_software_table_template}}
- | Mass storage
- | [[QUADSPI internal peripheral|QUADSPI]]
- |
- | [[MTD overview|Linux MTD framework]]
- | [[STM32CubeMP1 architecture|STM32Cube QUADSPI driver]]
- |
- |-
- |}
-====Peripheral configuration====
+* '''Linux<sup>&reg;</sup>''': [[MTD overview|MTD framework]] and driver ({{CodeSource | Linux kernel | drivers/spi/spi-stm32-qspi.c}})
-The firmware, running in the context to which the peripheral is assigned, applies the configuration that can be done alone via the [[STM32CubeMX]] tool for all internal peripherals and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.
+* '''STM32Cube''': [[STM32CubeMP15 Package architecture|QUADSPI HAL driver]] and {{CodeSource | STM32CubeMP1 | Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_qspi.h | header file of QUADSPI HAL module}}
+* '''TF-A BL2''': MTD frameworks ({{CodeSource | TF-A | drivers/mtd/}}) and driver ({{CodeSource | TF-A | drivers/st/spi/stm32_qspi.c}})
+* '''U-Boot''': MTD frameworks ({{CodeSource | U-Boot | drivers/mtd/}}) and drivers ({{CodeSource | U-Boot | drivers/spi/stm32_qspi.c}})
+==How to assign and configure the peripheral==
+The peripheral assignment can be done via the [[STM32CubeMX]] graphical tool (and manually completed if needed).<br />
+This tool also helps to configure the peripheral:
+* partial device trees (pin control and clock tree) generation for the OpenSTLinux software components,
+* HAL initialization code generation for the STM32CubeMPU Package.
+The configuration is applied by the firmware running in the context in which the peripheral is assigned.
-For Linux kernel configuration, please refer to [[QUADSPI device tree configuration]].
+For Linux kernel configuration, refer to [[QUADSPI device tree configuration]].
-====Peripherals assignment====
-===== On {{MicroprocessorDevice | device=13}} =====
-{{:STM32MP13_internal_peripherals_assignment_table_template}}
-<section begin=stm32mp13 />
- | rowspan="1" | Mass storage
- | rowspan="1" | [[QUADSPI internal peripheral|QUADSPI]]
- | QUADSPI
- | <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span>
- | <span title="assignable peripheral" style="font-size:21px">☐</span>
- | Assignment (single choice)
- |-
-<section end=stm32mp13 />
- |}
-===== On {{MicroprocessorDevice | device=15}} =====
-{{:STM32MP15_internal_peripherals_assignment_table_template}}
-<section begin=stm32mp15 />
- | rowspan="1" | Mass storage
- | rowspan="1" | [[QUADSPI internal peripheral|QUADSPI]]
- | QUADSPI
- |
- | <span title="assignable peripheral" style="font-size:21px">☐</span>
- | <span title="assignable peripheral" style="font-size:21px">☐</span>
- | Assignment (single choice)
- |-
-<section end=stm32mp15 />
- |}
-==References==
-<references/>
 <noinclude>
+[[Category:Mass storage peripherals]]
 {{ArticleBasedOnModel | Internal peripheral article model}}
-[[Category: Mass storage peripherals]]
 {{PublicationRequestId | 24667|  2022-09-26}}
 </noinclude>