1. Article purpose[edit source]
The purpose of this article is to
- briefly introduce the LPTIM peripheral and its main features
- indicate the level of security supported by this hardware block
- explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
- explain how to configure the LPTIM peripheral
2. Peripheral overview[edit source]
The LPTIM peripheral is a single channel low-power timer unit, that can continue to run even during low power modes when it selects a clock source that remains active in RCC.
2.1. Features[edit source]
Refer to STM32MP13 reference manuals or STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to know which features are really implemented.
The LPTIM peripheral is available in different configurations. Depending on the selected instance, it can act as
PWM, quadrature encoder[1],
external event counter or trigger source for other internal peripherals, like ADC[2], DFSDM[3] and DAC[4] (on STM32MP15x lines 
).
| LPTIM features | PWM | External event counter Trigger source |
Quadrature encoder |
|---|---|---|---|
| LPTIM1, LPTIM2 | 
|
|
|
| LPTIM3 |
|
|
|
| LPTIM4, LPTIM5 |
|
- On STM32MP13x lines , LPTIM3 can be used for RCC HSE clock source monitoring
2.2. Security support[edit source]
2.2.1. On STM32MP13x lines [edit source]
There are 5 instances of LPTIM:
- LPTIM instances 1, 4 and 5 are non-secure peripheral
- LPTIM instances 2 and 3 are secure (under ETZPC control)
2.2.2. On STM32MP15x lines [edit source]
The 5 LPTIM instances are a non-secure peripherals.
3. Peripheral usage and associated software[edit source]
3.1. Boot time[edit source]
The LPTIM is not used at boot time.
3.2. Runtime[edit source]
3.2.1. Overview[edit source]
3.2.1.1. On STM32MP13x lines [edit source]
LPTIM instances can be allocated to:
- the Arm® Cortex®-A7 secure to be used under OP-TEE
or
- the Arm® Cortex®-A7 non-secure to be used under Linux® with PWM, IIO, Counter or/and Clock events frameworks
3.2.1.2. On STM32MP15x lines [edit source]
LPTIM instances can be allocated to:
- the Arm® Cortex®-A7 non-secure to be used under Linux® with PWM, IIO, Counter or/and Clock events frameworks,
or
- the Arm® Cortex®-M4 to be used with STM32Cube MPU Package with LPTIM HAL driver
3.2.2. Software frameworks[edit source]
3.2.2.1. On STM32MP13x lines [edit source]
| Domain | Peripheral | Software components | Comment | |
|---|---|---|---|---|
| OP-TEE | Linux | |||
| Core/Timers | LPTIM | OP-TEE | PWM framework, IIO framework, Counter framework, Clock events framework |
|
3.2.2.2. On STM32MP15x lines [edit source]
| Domain | Peripheral | Software components | Comment | ||
|---|---|---|---|---|---|
| OP-TEE | Linux | STM32Cube | |||
| Core/Timers | LPTIM | PWM framework, IIO framework, Counter framework, Clock events framework |
STM32Cube LPTIM driver | ||
3.2.3. Peripheral configuration[edit source]
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be performed via STM32CubeMX tool for all internal peripherals. It can then be manually completed (especially for external peripherals) according to the information given in the corresponding software framework article.
For Linux kernel configuration, please refer to LPTIM device tree configuration and STM32 LPTIM Linux driver articles.
3.2.4. Peripheral assignment[edit source]
3.2.4.1. On STM32MP13x lines [edit source]
Click on the right to expand the legend...
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ☐ means that the peripheral can be assigned (☑) to the given runtime context.
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.
Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment | ||
|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) | |||
| Core/Timers | LPTIM | LPTIM1 | ☐ | ||
| LPTIM2 | ⬚ | ☐ | Assignment (single choice) | ||
| LPTIM3 | ☐ | ☐ | Assignment (single choice) LPTIM3 can be used for HSE monitoring | ||
| LPTIM4 | ☐ | ||||
| LPTIM5 | ☐ | Assignment (single choice) | |||
3.2.4.2. On STM32MP15x lines [edit source]
Click on the right to expand the legend...
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ☐ means that the peripheral can be assigned (☑) to the given runtime context.
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.
Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment | |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) |
Cortex-M4 (STM32Cube) | |||
| Core/Timers | LPTIM | LPTIM1 | ☐ | ☐ | Assignment (single choice) | |
| LPTIM2 | ☐ | ☐ | Assignment (single choice) | |||
| LPTIM3 | ☐ | ☐ | Assignment (single choice) | |||
| LPTIM4 | ☐ | ☐ | Assignment (single choice) | |||
| LPTIM5 | ☐ | ☐ | Assignment (single choice) | |||
4. References[edit source]
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.