1. Article purpose[edit source]
The purpose of this article is to:
- briefly introduce the DMAMUX peripheral and its main features
- indicate the level of security supported by this hardware block
- explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
- explain, when necessary, how to configure the DMAMUX peripheral.
2. Peripheral overview[edit source]
The DMAMUX peripheral is used to perform requestor line (or device controller) selection for each channel from DMA instances:
- In STM32MP13x lines
there is a first DMAMUX instance to cover both DMA1 and DMA2, and second DMAMUX instance to cover DMA3. - In STM32MP15x lines there is a single DMAMUX instance to cover both DMA1 and DMA2.
2.1. Features[edit source]
Refer to STM32MP13 reference manuals or STM32MP15 reference manuals for the complete feature list and to the software components, introduced below, to see which features are implemented.
2.2. Security support[edit source]
2.2.1. On STM32MP13x lines [edit source]
The DMAMUX1 is a non-secure peripheral. The DMAMUX2 is a secure peripheral.
2.2.2. On STM32MP15x lines [edit source]
The DMAMUX is a non secure peripheral.
3. Peripheral usage and associated software[edit source]
3.1. Boot time[edit source]
The DMAMUX is not used at boot time.
3.2. Runtime[edit source]
3.2.1. Overview[edit source]
3.2.1.1. On STM32MP13x lines [edit source]
The DMAMUX1 manages DMA1 and DMA2 requestor line selection, so it can be assigned to the Arm® Cortex®-A7 non-secure context to be controlled in Linux® by the dmaengine framework. The DMAMUX2 manages DMA3 requestor line selection, so it can be assigned to the Arm® Cortex®-A7 secure context to be controlled by a DMAMUX OP-TEE driver, not supported yet by OpenSTLinux.
3.2.1.2. On STM32MP15x lines [edit source]
The DMAMUX manages DMA1 and DMA2 requestor line selection via different registers so it is possible to concurrently access to DMAMUX from Cortex®-A7 non-secure and Cortex®-M4 contexts, as far as each core is only configuring the requestor lines for the DMA instances (DMA1 and/or DMA2) assigned to itself.
Finally, DMAMUX can be allocated to:
- the Arm® Cortex®-A7 non-secure core to be controlled in Linux® by the dmaengine framework
or
- the Arm® Cortex®-M4 to be controlled in STM32Cube MPU Package by the DMA HAL driver
3.2.2. Software frameworks[edit source]
3.2.2.1. On STM32MP13x lines [edit source]
| Domain | Peripheral | Software components | Comment | |
|---|---|---|---|---|
| OP-TEE | Linux | |||
| Core/DMA | DMAMUX | OP-TEE DMAMUX driver | Linux dmaengine framework | |
3.2.2.2. On STM32MP15x lines [edit source]
| Domain | Peripheral | Software components | Comment | ||
|---|---|---|---|---|---|
| OP-TEE | Linux | STM32Cube | |||
| Core/DMA | DMAMUX | Linux dmaengine framework | STM32Cube DMAMUX driver | ||
3.2.3. Peripheral configuration[edit source]
The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration can be done alone via the STM32CubeMX tool for all internal peripherals, and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.
3.2.4. Peripheral assignment[edit source]
3.2.4.1. On STM32MP13x lines [edit source]
Click on the right to expand the legend...
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ☐ means that the peripheral can be assigned (☑) to the given runtime context.
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.
Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment | ||
|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) | |||
| Core/DMA | DMAMUX | DMAMUX1 | ☐ | Assignment (single choice) | |
| DMAMUX2 | ⬚ | Assignment (single choice) | |||
3.2.4.2. On STM32MP15x lines [edit source]
Click on the right to expand the legend...
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ☐ means that the peripheral can be assigned (☑) to the given runtime context.
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.
Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment | |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) |
Cortex-M4 (STM32Cube) | |||
| Core/DMA | DMAMUX | DMAMUX | ☐ | ☐ | Shareable (multiple choices supported) | |
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.