STGEN internal peripheral

1. Article purpose

The purpose of this article is to:

• briefly introduce the STGEN peripheral and its main features
• indicate the level of security supported by this hardware block
• explain how it can be allocated to the three runtime contexts and linked to the corresponding software components
• explain, when necessary, how to configure the STGEN peripheral.

2. Peripheral overview

The STGEN peripheral provides the reference clock used by the Arm^® Cortex^®-A7 generic timer for its counters, including the system tick generation.

It is clocked by ACLK (the AXI bus clock), so caution is needed when this clock is changed; otherwise the operating system (running on the Cortex-A7) might run with a varying reference clock.

2.1. Features

Refer to the STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.

2.2. Security support

The STGEN is a single-instance peripheral that can be accessed via the two following register sets:

• STGENC for the control. That is, a secure port (under ETZPC control).
• STGENR for the read-only access. That is, a non secure port.

3. Peripheral usage and associated software

3.1. Boot time

The STGEN is first initialized by the ROM code, then updated by the FSBL (see Boot chains overview) once the clock tree is set up.

3.2. Runtime

3.2.1. Overview

Linux^® and OP-TEE use the Arm Cortex-A7 generic timer that gets its counter from the STGEN, but this is transparent at run time.

Hence there is no runtime allocation decision for this peripheral: both contexts are selected by default.

3.2.2. Software frameworks

Internal peripherals software table template

| Core
| STGEN
| see comment
| see comment
| 
| Not applicable as the STGEN peripheral is configured at boot time and not accessed at runtime
|-
|}

3.2.4. Peripheral assignment

Internal peripherals assignment table template

| rowspan="1" | Core
| rowspan="1" | STGEN
| STGEN
| ✓
| ✓
|
|
|-

|}