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==Article purpose== | ==Article purpose== | ||
The purpose of this article is to | The purpose of this article is to provide information on the Arm<sup>®</sup> CoreSight<sup>™</sup> hardware subsystem.<br /> | ||
It explains what are the principle peripherals of this subsystem.<br /> | It explains what are the principle peripherals of this subsystem.<br /> | ||
==Peripheral overview== | ==Peripheral overview== | ||
Arm<sup>®</sup> '''CoreSight<sup>™</sup> ''' products include a wide range of trace macrocells for Arm<sup>®</sup> processors, | Arm<sup>®</sup> '''CoreSight<sup>™</sup> ''' products include | ||
* a wide range of trace macrocells for Arm<sup>®</sup> processors, | |||
[[File:Coresight_overview.png|thumb|center|766px|alt=Alternate text| | To enable the debug and trace of the most complex, multi-core SoCs, Arm<sup>®</sup> '''CoreSight<sup>™</sup> ''' products include | ||
* a system and software instrumentation, | |||
* and a comprehensive set of IP blocks. | |||
Arm<sup>®</sup> has defined an open CoreSight architecture to allow SoC designers to add "debug and trace" capabilities for other IP cores in to the CoreSight<sup>™</sup> infrastructure.<br /> | |||
[[File:Coresight_overview.png|thumb|center|766px|alt=Alternate text|CoreSight overview of STM32MP15. Check the [[#Features | Reference Manual]] for the other devices]] | |||
===Components description=== | ===Components description=== | ||
| Line 29: | Line 35: | ||
| APB-AP: APB access port || {{Y}} || {{Y}} | | APB-AP: APB access port || {{Y}} || {{Y}} | ||
|- | |- | ||
| ITM: Instrumentation Trace Macrocell || {{Y}} || {{Y}} | | ITM: Instrumentation Trace Macrocell || {{N}} || {{Y}} | ||
|- | |||
| DWT: Data Watchpoint and Trace || {{N}} || {{Y}} | |||
|- | |- | ||
| | | FPB: Flash Patch and Breakpoint || {{N}} || {{Y}} | ||
|- | |- | ||
| ETM: [[ETM internal peripheral|Embedded Trace Macrocell]] || {{Y}} || {{Y}} | | ETM: [[ETM internal peripheral|Embedded Trace Macrocell]] || {{Y}} || {{Y}} | ||
| Line 53: | Line 61: | ||
===Features=== | ===Features=== | ||
Refer to the '''Debug support (DBG)''' chapter of [[STM32 MPU resources#Reference manuals|reference manuals]] corresponding to the STM32 MPU, you use, for the complete list of features, and to the software components, introduced above, to see which features are really implemented.<br> | |||
<br> | |||
==References== | ==References== | ||
| Line 63: | Line 69: | ||
[[Category:Arm CoreSight peripherals]] | [[Category:Arm CoreSight peripherals]] | ||
{{NoIndex}} | {{NoIndex}} | ||
{{PublicationRequestId | 20002 | 2021-05-12 | }} | |||
</noinclude> | </noinclude> | ||
Latest revision as of 18:39, 8 June 2023
1. Article purpose
The purpose of this article is to provide information on the Arm® CoreSight™ hardware subsystem.
It explains what are the principle peripherals of this subsystem.
2. Peripheral overview
Arm® CoreSight™ products include
- a wide range of trace macrocells for Arm® processors,
To enable the debug and trace of the most complex, multi-core SoCs, Arm® CoreSight™ products include
- a system and software instrumentation,
- and a comprehensive set of IP blocks.
Arm® has defined an open CoreSight architecture to allow SoC designers to add "debug and trace" capabilities for other IP cores in to the CoreSight™ infrastructure.
CoreSight overview of STM32MP15. Check the Reference Manual for the other devices
2.1. Components description
The debug features are based on Arm® CoreSight™ components
| Arm® CoreSight™ components | STM32MP13x lines 
|
STM32MP15x lines
|
|---|---|---|
| SWJ-DP: JTAG/Serial-wire debug port |  |
|
| AXI-AP: AXI access port | |
|
| AHB-AP: AHB access port |  |
|
| APB-AP: APB access port | |
|
| ITM: Instrumentation Trace Macrocell | |
|
| DWT: Data Watchpoint and Trace | |
|
| FPB: Flash Patch and Breakpoint | |
|
| ETM: Embedded Trace Macrocell | |
|
| ETF: Embedded Trace FIFO | |
|
| TPIU: Trace Port Interface Unit | |
|
| SWO: Serial Wire Output | |
|
| CTI: Cross Trigger Interface | |
|
| CTM: Cross Trigger Matrix | |
|
| TSGEN: Timestamp Generator | |
|
| STM: System Trace Macrocell | |
|
More information about these components can be found in the Arm® website [1]
2.2. Features
Refer to the Debug support (DBG) chapter of reference manuals corresponding to the STM32 MPU, you use, for the complete list of features, and to the software components, introduced above, to see which features are really implemented.
3. References