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<noinclude>{{ApplicableFor | |||
|MPUs list=STM32MP13x, STM32MP15x | |||
|MPUs checklist=STM32MP13x,STM32MP15x | |||
}}</noinclude> | |||
==Article purpose== | ==Article purpose== | ||
The purpose of this article is to | The purpose of this article is to | ||
| Line 7: | Line 12: | ||
==Peripheral overview== | ==Peripheral overview== | ||
The Quad-SPI interface ('''QUADSPI''' peripheral) | The Quad-SPI interface ('''QUADSPI''' peripheral) interfaces the processor with serial NOR flash and serial NAND flash memories. <br /> | ||
It supports: | It supports: | ||
* Single, | * Single, Dual- or Quad-SPI flash memories | ||
* A dual-flash mode, allowing to | * A dual-flash mode, allowing to aggregate two flash memories into a virtual-single one | ||
* Dual data rate and memory-mapped modes. | * Dual data rate and memory-mapped modes. | ||
===Features=== | ===Features=== | ||
Refer to [[STM32MP13 resources#Reference manuals|STM32MP13 reference manuals]] or [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list | Refer to [[STM32MP13 resources#Reference manuals|STM32MP13 reference manuals]] or [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete feature list and to the software components introduced below to know the implemented features. | ||
===Security support=== | ===Security support=== | ||
| Line 20: | Line 25: | ||
The QUADSPI is a '''secure''' peripheral (under [[ETZPC_internal_peripheral|ETZPC]] control). | The QUADSPI is a '''secure''' peripheral (under [[ETZPC_internal_peripheral|ETZPC]] control). | ||
==== On {{MicroprocessorDevice | device=15}} ==== | ==== On {{MicroprocessorDevice | device=15}} ==== | ||
The QUADSPI is a '''non secure''' peripheral. | The QUADSPI is a '''non-secure''' peripheral. | ||
==Using the peripheral - associated software== | ==Using the peripheral-associated software== | ||
===Boot time=== | ===Boot time=== | ||
QUADSPI instance is boot device that | QUADSPI instance is a boot device that supports serial boot for flash programming with [[STM32CubeProgrammer]]. | ||
===Runtime=== | ===Runtime=== | ||
====Overview==== | ====Overview==== | ||
Allocation of the QUADSPI instances can be: | |||
* | * The Arm<sup>®</sup> Cortex<sup>®</sup>-A7 secure context, on {{MicroprocessorDevice | device=13}} only, but this is not supported in OpenSTLinux. | ||
or | or | ||
* | * The Arm<sup>®</sup> Cortex<sup>®</sup>-A7 non-secure core to be controlled in Linux<sup>®</sup> by the [[MTD overview|MTD]] framework | ||
or | or | ||
* | * The Arm<sup>®</sup> Cortex<sup>®</sup>-M4, on {{MicroprocessorDevice | device=15}} only, to be controlled in STM32Cube MPU Package by [[STM32CubeMP1 architecture|QUADSPI HAL driver]] | ||
Chapter [[# | Chapter [[#Peripherals assignment]] describes which peripheral instances can be assigned to which context. | ||
====Software frameworks==== | ====Software frameworks==== | ||
===== On {{MicroprocessorDevice | device=13}} ===== | ===== On {{MicroprocessorDevice | device=13}} ===== | ||
{{:STM32MP13 internal peripherals software table template}} | {{: STM32MP13 internal peripherals software table template}} | ||
| Mass storage | | Mass storage | ||
| [[QUADSPI internal peripheral|QUADSPI]] | | [[QUADSPI internal peripheral|QUADSPI]] | ||
| Line 59: | Line 64: | ||
====Peripheral configuration==== | ====Peripheral configuration==== | ||
The | The firmware, running in the context to which the peripheral is assigned, applies the configuration that can be done alone via the [[STM32CubeMX]] tool for all internal peripherals and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article. | ||
For Linux kernel configuration, please refer to [[QUADSPI device tree configuration]]. | For Linux kernel configuration, please refer to [[QUADSPI device tree configuration]]. | ||
==== | ====Peripherals assignment==== | ||
===== On {{MicroprocessorDevice | device=13}} ===== | ===== On {{MicroprocessorDevice | device=13}} ===== | ||
{{:STM32MP13_internal_peripherals_assignment_table_template}} | {{:STM32MP13_internal_peripherals_assignment_table_template}} | ||
| Line 96: | Line 101: | ||
{{ArticleBasedOnModel | Internal peripheral article model}} | {{ArticleBasedOnModel | Internal peripheral article model}} | ||
[[Category:Mass storage peripherals]] | [[Category:Mass storage peripherals]] | ||
{{PublicationRequestId | 24667| 2022-09-26}} | |||
</noinclude> | </noinclude> | ||
Latest revision as of 09:52, 27 October 2022
1. Article purpose[edit source]
The purpose of this article is to
- briefly introduce the QUADSPI peripheral and its main features
- indicate the level of security supported by this hardware block
- explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
- explain, when needed, how to configure the QUADSPI peripheral.
2. Peripheral overview[edit source]
The Quad-SPI interface (QUADSPI peripheral) interfaces the processor with serial NOR flash and serial NAND flash memories.
It supports:
- Single, Dual- or Quad-SPI flash memories
- A dual-flash mode, allowing to aggregate two flash memories into a virtual-single one
- Dual data rate and memory-mapped modes.
2.1. Features[edit source]
Refer to STM32MP13 reference manuals or STM32MP15 reference manuals for the complete feature list and to the software components introduced below to know the implemented features.
2.2. Security support[edit source]
2.2.1. On STM32MP13x lines 
[edit source]
The QUADSPI is a secure peripheral (under ETZPC control).
2.2.2. On STM32MP15x lines [edit source]
The QUADSPI is a non-secure peripheral.
3. Using the peripheral-associated software[edit source]
3.1. Boot time[edit source]
QUADSPI instance is a boot device that supports serial boot for flash programming with STM32CubeProgrammer.
3.2. Runtime[edit source]
3.2.1. Overview[edit source]
Allocation of the QUADSPI instances can be:
- The Arm® Cortex®-A7 secure context, on STM32MP13x lines only, but this is not supported in OpenSTLinux.
or
- The Arm® Cortex®-A7 non-secure core to be controlled in Linux® by the MTD framework
or
- The Arm® Cortex®-M4, on STM32MP15x lines only, to be controlled in STM32Cube MPU Package by QUADSPI HAL driver
Chapter #Peripherals assignment describes which peripheral instances can be assigned to which context.
3.2.2. Software frameworks[edit source]
3.2.2.1. On STM32MP13x lines [edit source]
| Domain | Peripheral | Software components | Comment | |
|---|---|---|---|---|
| OP-TEE | Linux | |||
| Mass storage | QUADSPI | Linux MTD framework | ||
3.2.2.2. On STM32MP15x lines [edit source]
| Domain | Peripheral | Software components | Comment | ||
|---|---|---|---|---|---|
| OP-TEE | Linux | STM32Cube | |||
| Mass storage | QUADSPI | Linux MTD framework | STM32Cube QUADSPI driver | ||
3.2.3. Peripheral configuration[edit source]
The firmware, running in the context to which the peripheral is assigned, applies the configuration that can be done alone via the STM32CubeMX tool for all internal peripherals and then manually completed (particularly for external peripherals), according to the information given in the corresponding software framework article.
For Linux kernel configuration, please refer to QUADSPI device tree configuration.
3.2.4. Peripherals assignment[edit source]
3.2.4.1. On STM32MP13x lines [edit source]
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ☐ means that the peripheral can be assigned (☑) to the given runtime context.
- ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
- ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.
Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment | ||
|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) | |||
| Mass storage | QUADSPI | QUADSPI | ⬚ | ☐ | Assignment (single choice) |
3.2.4.2. On STM32MP15x lines [edit source]
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ☐ means that the peripheral can be assigned (☑) to the given runtime context.
- ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.
Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment | |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) |
Cortex-M4 (STM32Cube) | |||
| Mass storage | QUADSPI | QUADSPI | ☐ | ☐ | Assignment (single choice) | |
4. References[edit source]
Arm® is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 