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<noinclude>{{ApplicableFor | |||
|MPUs list=STM32MP13x, STM32MP15x | |||
|MPUs checklist=STM32MP13x, STM32MP15x | |||
}}</noinclude> | |||
==Article purpose== | ==Article purpose== | ||
The purpose of this article is to: | The purpose of this article is to: | ||
| Line 5: | Line 9: | ||
==Peripheral overview== | ==Peripheral overview== | ||
The Arm Cortex-A7 can be instantiated several times into a single cluster. | The Arm Cortex-A7 can be instantiated several times into a single cluster: | ||
* The [[STM32MP13 microprocessor | STM32MP13]] main processor is a Cortex-A7 cluster embedding a single core. | |||
The [[STM32MP15 microprocessor | STM32MP15]] main processor is a Cortex-A7 cluster embedding one or two core(s), depending on the selected [[STM32MP15_microprocessor#STM32MP15x_lines | line]]. | * The [[STM32MP15 microprocessor | STM32MP15]] main processor is a Cortex-A7 cluster embedding one or two core(s), depending on the selected [[STM32MP15_microprocessor#STM32MP15x_lines | line]]. | ||
===Features=== | ===Features=== | ||
The Cortex-A7 is a 32-bit processor that belongs to ARMv7-VE architecture family. ARMv7-VE corresponds to the ARMv7-A architecture, with virtual extensions. Among a wide range of features, it includes a memory management unit (MMU), a separate L1 cache and a unified L2 cache in order to efficiently support rich operating systems such as Linux, with a high level of performance. | The Cortex-A7 is a 32-bit processor that belongs to ARMv7-VE architecture family. ARMv7-VE corresponds to the ARMv7-A architecture, with virtual extensions. Among a wide range of features, it includes a memory management unit (MMU), a separate L1 cache and a unified L2 cache in order to efficiently support rich operating systems such as Linux, with a high level of performance. | ||
Refer to the [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features. | Refer to the [[STM32MP13 resources#Reference manuals|STM32MP13 reference manuals]] or the [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features. | ||
===Security support=== | ===Security support=== | ||
The Cortex-A7 supports a non-secure and secure modes that define two [[:Category:STM32_MPU_microprocessor_devices#Hardware_execution_contexts | hardware execution contexts]], named Cortex-A7 non-secure and Cortex-A7 secure. | The Cortex-A7 supports a non-secure and a secure modes that define two [[:Category:STM32_MPU_microprocessor_devices#Hardware_execution_contexts | hardware execution contexts]], named Cortex-A7 non-secure and Cortex-A7 secure. | ||
==Peripheral usage and associated software== | ==Peripheral usage and associated software== | ||
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===Boot time=== | ===Boot time=== | ||
As soon as the STM32MP1 is powered up, the Cortex-A7 starts to execute the [[ | As soon as the STM32MP1 is powered up, the Cortex-A7 starts to execute the [[STM32 MPU ROM code overview | ROM code]], which is the first stage of the [[Boot chain overview | boot chain]]. It then executes the FSBL [[TF-A overview | TF-A]] in secure mode before jumping to the SSBL [[U-Boot overview | U-Boot]] in non-secure mode. | ||
===Runtime=== | ===Runtime=== | ||
====Overview==== | ====Overview==== | ||
The Cortex-A7 runs [[ | The Cortex-A7 runs [[STM32 MPU Linux kernel overview | Linux]] in non-secure mode and [[OP-TEE overview | OP-TEE]] in secure mode. Linux is executed in SMP mode on the dual-core versions, as explained in the [[#Peripheral overview|above]]. | ||
====Software frameworks==== | ====Software frameworks==== | ||
{{: | {{:STM32MP15_internal_peripherals_software_table_template}} | ||
| Ecosystem | | Ecosystem | ||
| [[Arm_Cortex-A7 | Cortex-A7]] | | [[Arm_Cortex-A7 | Cortex-A7]] | ||
| [[OP-TEE overview | OP-TEE]] | | [[OP-TEE overview | OP-TEE]] | ||
| [[ | | [[STM32 MPU Linux kernel overview | Linux]] | ||
| | | | ||
| | | | ||
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[[Category:Arm processors]] | [[Category:Arm processors]] | ||
{{PublicationRequestId | 19285 | 2021-03-10 | }} | {{PublicationRequestId | 19285 | 2021-03-10 | }} | ||
<noinclude> | </noinclude> | ||
Latest revision as of 11:35, 24 October 2022
1. Article purpose
The purpose of this article is to:
- briefly introduce the Arm® Cortex®-A7 core and its main features
- indicate the level of security supported by this processor
2. Peripheral overview
The Arm Cortex-A7 can be instantiated several times into a single cluster:
- The STM32MP13 main processor is a Cortex-A7 cluster embedding a single core.
- The STM32MP15 main processor is a Cortex-A7 cluster embedding one or two core(s), depending on the selected line.
2.1. Features
The Cortex-A7 is a 32-bit processor that belongs to ARMv7-VE architecture family. ARMv7-VE corresponds to the ARMv7-A architecture, with virtual extensions. Among a wide range of features, it includes a memory management unit (MMU), a separate L1 cache and a unified L2 cache in order to efficiently support rich operating systems such as Linux, with a high level of performance.
Refer to the STM32MP13 reference manuals or the STM32MP15 reference manuals for the complete list of features.
2.2. Security support
The Cortex-A7 supports a non-secure and a secure modes that define two hardware execution contexts, named Cortex-A7 non-secure and Cortex-A7 secure.
3. Peripheral usage and associated software
All the software components executed by the Cortex-A7, at boot time and at runtime, constitute the OpenSTLinux distribution.
3.1. Boot time
As soon as the STM32MP1 is powered up, the Cortex-A7 starts to execute the ROM code, which is the first stage of the boot chain. It then executes the FSBL TF-A in secure mode before jumping to the SSBL U-Boot in non-secure mode.
3.2. Runtime
3.2.1. Overview
The Cortex-A7 runs Linux in non-secure mode and OP-TEE in secure mode. Linux is executed in SMP mode on the dual-core versions, as explained in the above.
3.2.2. Software frameworks
| Domain | Peripheral | Software components | Comment | ||
|---|---|---|---|---|---|
| OP-TEE | Linux | STM32Cube | |||
| Ecosystem | Cortex-A7 | OP-TEE | Linux | ||
3.2.3. Peripheral configuration
The Cortex-A7 configuration is done by the various components running on it, according to build-time parameters, and also information from the device tree.
3.2.4. Peripheral assignment
The Cortex-A7 is the main processor supporting Cortex-A7 secure and Cortex-A7 non-secure contexts. It therefore cannot be assigned but, it manages all the peripherals assigned to those contexts.
4. How to go further
Refer to Arm website[1] for more detailed information on this core.
5. References