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<noinclude>
<noinclude>{{ApplicableFor
{{ArticleBasedOnModel| [[Internal peripheral article model]]}}
|MPUs list=STM32MP13x, STM32MP15x
{{ArticleMainWriter|FabriceG}}
|MPUs checklist=STM32MP13x,STM32MP15x
{{ReviewersList|GeraldB, BenjaminG, LionelD}}
}}</noinclude>
{{ArticleApprovedVersion| FabriceG | GeraldB | FabriceG - 04Jul'18 | AlainF - 03Jul'18 - 7895 | 16Oct'18 }}
[[Category:Timers peripherals]]
</noinclude>
 
==Article purpose==
==Article purpose==
The purpose of this article is to
The purpose of this article is to
* briefly introduce the '''TIM''' peripheral and its main features
* briefly introduce the '''TIM''' peripheral and its main features
* indicate the level of security supported by this hardware block
* indicate the level of security supported by this hardware block
* explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
* explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
* explain how to configure the TIM peripheral
* explain how to configure the TIM peripheral


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The TIM can provide: PWM with complementary output and dead-time insertion, break detection,
The TIM can provide: PWM with complementary output and dead-time insertion, break detection,
input capture<ref name="input_capture">[https://en.wikipedia.org/wiki/Input_capture Input capture]</ref>,
input capture<ref name="input_capture">[https://en.wikipedia.org/wiki/Input_capture Input capture]</ref>,
quadrature encoder<ref name="quadrature_encoder">[https://en.wikipedia.org/wiki/Rotary_encoder#Incremental_encoder Quadrature encoder]</ref> interface (typically used for rotary encoders), trigger source for other internal peripherals like: ADC<ref name="adc_internal">[[ADC internal peripheral]]</ref>, DAC<ref name="dac_internal">[[DAC internal peripheral]]</ref>, DFSDM<ref name="dfsdm_internal">[[DFSDM internal peripheral]]</ref>.
quadrature encoder<ref name="quadrature_encoder">[https://en.wikipedia.org/wiki/Rotary_encoder#Incremental_encoder Quadrature encoder]</ref> interface (typically used for rotary encoders), trigger source for other internal peripherals like: ADC<ref name="adc_internal">[[ADC internal peripheral]]</ref>, DFSDM<ref name="dfsdm_internal">[[DFSDM internal peripheral]]</ref>. The full list can be found in Peripherals Interconnect matrix in the reference manual.
 
===Features===
===Features===
The '''TIM''' peripheral is available in different configurations, depending on the selected instance :
The '''TIM''' peripheral is available in different configurations, depending on the selected instance :
Line 27: Line 24:
* TIM15, TIM16 and TIM17 are also general-purpose timers, with 2 (TIM15) or 1 (TIM16 and TIM17) independent channels. Compare to TIM12, TIM13 and TIM14, this configuration brings some features that are very useful for motor control (like break function, DMA burst mode control, complementary output with dead-time insertion, ...)
* TIM15, TIM16 and TIM17 are also general-purpose timers, with 2 (TIM15) or 1 (TIM16 and TIM17) independent channels. Compare to TIM12, TIM13 and TIM14, this configuration brings some features that are very useful for motor control (like break function, DMA burst mode control, complementary output with dead-time insertion, ...)
* TIM6 and TIM7 are basic timers
* TIM6 and TIM7 are basic timers
Refer to [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to know which features are really implemented.
Refer to [[STM32MP13 resources#Reference manuals|STM32MP13 reference manuals]] or [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to know which features are really implemented.
 
{{ReviewsComments | [[User:Olivier Moysan|Olivier Moysan]] ([[User talk:Olivier Moysan|talk]]) 15:39, 29 November 2021 (CET) - Probably a table would be more readable here, as already done in LPTIM article. Channel number, resolution and encoder support could be documented in this table.<br>
Gerald: I agree, this could be done later on}}


===Security support===
===Security support===
The TIM is a '''non-secure''' peripheral.
{{ReviewsComments | [[User:Olivier Moysan|Olivier Moysan]] ([[User talk:Olivier Moysan|talk]]) 15:39, 29 November 2021 (CET) - This section is redundant with Peripheral assignment section. So I suggest to remove it.<br>
Gerald: it is indeed redundant but this is how we agreed the template a long time ago so thanks to keep this paragraph}}
 
===== On {{MicroprocessorDevice | device=13}} =====
There are 14 instances of TIM:
* TIM instances 1, 2, 3, 4, 5, 6, 7 and 8 are '''non-secure''' peripheral
* TIM instances 12, 13, 14, 15, 16 and 17 are '''secure''' (under [[ETZPC_internal_peripheral|ETZPC]] control)
===== On {{MicroprocessorDevice | device=15}} =====
The 14 instances of TIM are '''non-secure''' peripherals.


==Peripheral usage and associated software==
==Peripheral usage and associated software==
Line 38: Line 46:
===Runtime===
===Runtime===
====Overview====
====Overview====
===== On {{MicroprocessorDevice | device=13}} =====
'''TIM12''' and/or '''TIM15''' can be allocated to:
'''TIM12''' and/or '''TIM15''' can be allocated to:
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure core to be controlled in the secure monitor ([[TF-A overview|TF-A]] or [[OP-TEE overview|OP-TEE]]), to perform HSI and CSI calibrations<ref>[[How to activate HSI and CSI oscillators calibration]]</ref> in [[RCC internal peripheral|RCC]].
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure core to be controlled in the secure monitor ([[OP-TEE overview|OP-TEE]]), to perform HSI and CSI calibrations<ref name="calib"/> in [[RCC internal peripheral|RCC]].
<br />
'''TIM13''', '''TIM14''', '''TIM16''' and '''TIM17''' can also be allocated to the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure context, but there is no support for them in [[OP-TEE overview|OP-TEE]] yet.<br>
'''All TIM instances''' can be allocated to:
'''All TIM instances''' can be allocated to:
*the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure to be controlled in Linux<sup>&reg;</sup> by the [[PWM overview|PWM]] and/or the [[IIO overview|IIO]] frameworks.
*the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure to be controlled in Linux<sup>&reg;</sup> by the [[PWM overview|PWM]], the [[IIO overview|IIO]], and/or the ''Counter'' frameworks.
 
{{Info | RCC<ref name="rcc">[[RCC internal peripheral]]</ref> owns one prescaler per '''TIM group''' corresponding to '''APB1''', '''APB2''' and '''APB6''' buses: TIMG1PRE, TIMG2PRE and TIMG3PRE, respectively. TIMG3PRE is securable in RCC. The allocation to Cortex-A7 contexts should ideally be done on a per group basis to get independent clocking setup on each side, this is why the TIM instances groups are shown in the summary table below ([[#Peripheral assignment]])}}
 
===== On {{MicroprocessorDevice | device=15}} =====
'''TIM12''' and/or '''TIM15''' can be allocated to:
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure core to be controlled in the secure monitor ([[TF-A overview|TF-A]] or [[OP-TEE overview|OP-TEE]]), to perform HSI and CSI calibrations<ref name="calib"/> in [[RCC internal peripheral|RCC]].
'''All TIM instances''' can be allocated to:
*the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure to be controlled in Linux<sup>&reg;</sup> by the [[PWM overview|PWM]], the [[IIO overview|IIO]], and/or the ''Counter'' frameworks.
or
or
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 to be controlled in STM32Cube MPU Package by [[STM32CubeMP1 architecture|TIM HAL driver]]
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 to be controlled in STM32Cube MPU Package by [[STM32CubeMP1 architecture|TIM HAL driver]]
<br />


Note that RCC<ref name="rcc">[[RCC internal peripheral]]</ref> owns one prescaler per '''TIM group''' corresponding to '''APB1''' and '''APB2''' buses: TIMG1PRE and TIMG2PRE, respectively. The allocation to Cortex-A7 or the Cortex-M4 should ideally be done on a per group basis to get independent clocking setup on each side, this is why the TIM instances groups are shown in the summary table below ([[#Peripheral assignment]]).
{{Info | RCC<ref name="rcc">[[RCC internal peripheral]]</ref> owns one prescaler per '''TIM group''' corresponding to '''APB1''' and '''APB2''' buses: TIMG1PRE and TIMG2PRE, respectively. The allocation to Cortex-A7 or the Cortex-M4 should ideally be done on a per group basis to get independent clocking setup on each side, this is why the TIM instances groups are shown in the summary table below ([[#Peripheral assignment]])}}


====Software frameworks====
====Software frameworks====
{{:Internal_peripherals_software_table_template}}
===== On {{MicroprocessorDevice | device=13}} =====
{{:STM32MP13 internal_peripherals_software_table_template}}
| Core/Timers
| [[TIM internal peripheral|TIM]]
| [[OP-TEE_overview|OP-TEE TIM driver]]
| [[PWM overview|PWM framework]]<br>[[IIO overview|IIO framework]],<br>''Counter'' framework
|
|-
|}
===== On {{MicroprocessorDevice | device=15}} =====
{{:STM32MP15_internal_peripherals_software_table_template}}
  | Core/Timers
  | Core/Timers
  | [[TIM internal peripheral|TIM]]
  | [[TIM internal peripheral|TIM]]
  | [[TF-A_overview|TF-A TIM driver]]<br />[[OP-TEE_overview|OP-TEE TIM driver]]
  | [[TF-A_overview|TF-A TIM driver]]<br />[[OP-TEE_overview|OP-TEE TIM driver]]
  | [[PWM overview|Linux PWM framework]]<br>[[IIO overview|Linux IIO framework]]
  | [[PWM overview|PWM framework]]<br>[[IIO overview|IIO framework]],<br>''Counter'' framework
  | [[STM32CubeMP1 architecture|STM32Cube TIM driver]]
  | [[STM32CubeMP1 architecture|STM32Cube TIM driver]]
  |
  |
Line 66: Line 92:


====Peripheral assignment====
====Peripheral assignment====
{{:Internal_peripherals_assignment_table_template}}
===== On {{MicroprocessorDevice | device=13}} =====
<onlyinclude>
{{:STM32MP13_internal_peripherals_assignment_table_template}}
<section begin=stm32mp13 />
| rowspan="14" | Core/Timers
| rowspan="14" | [[TIM internal peripheral|TIM]]
| TIM1 (APB2 group)
|
| <span title="assignable peripheral" style="font-size:21px">☐</span>
|
|-
| TIM2 (APB1 group)
|
| <span title="assignable peripheral" style="font-size:21px">☐</span>
|
|-
| TIM3 (APB1 group)
|
| <span title="assignable peripheral" style="font-size:21px">☐</span>
|
|-
| TIM4 (APB1 group)
|
| <span title="assignable peripheral" style="font-size:21px">☐</span>
|
|-
| TIM5 (APB1 group)
|
| <span title="assignable peripheral" style="font-size:21px">☐</span>
|
|-
| TIM6 (APB1 group)
|
| <span title="assignable peripheral" style="font-size:21px">☐</span>
|
|-
| TIM7 (APB1 group)
|
| <span title="assignable peripheral" style="font-size:21px">☐</span>
|
|-
| TIM8 (APB2 group)
|
| <span title="assignable peripheral" style="font-size:21px">☐</span>
|
|-
| TIM12 (APB6 group)
| <span title="assignable peripheral" style="font-size:21px">☐</span>
| <span title="assignable peripheral" style="font-size:21px">☐</span>
| Assignment (single choice)<br>TIM12 or TIM15 can be used for HSI/CSI calibration<ref name="calib">[[How to activate HSI and CSI oscillators calibration]]</ref>
|-
| TIM13 (APB6 group)
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span>
| <span title="assignable peripheral" style="font-size:21px">☐</span>
| Assignment (single choice)
|-
| TIM14 (APB6 group)
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span>
| <span title="assignable peripheral" style="font-size:21px">☐</span>
| Assignment (single choice)
|-
| TIM15 (APB6 group)
| <span title="assignable peripheral" style="font-size:21px">☐</span>
| <span title="assignable peripheral" style="font-size:21px">☐</span>
| Assignment (single choice)<br>TIM12 or TIM15 can be used for HSI/CSI calibration<ref name="calib"/>
|-
| TIM16 (APB6 group)
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span>
| <span title="assignable peripheral" style="font-size:21px">☐</span>
| Assignment (single choice)
|-
| TIM17 (APB6 group)
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span>
| <span title="assignable peripheral" style="font-size:21px">☐</span>
| Assignment (single choice)
|-
<section end=stm32mp13 />
|}
===== On {{MicroprocessorDevice | device=15}} =====
{{:STM32MP15_internal_peripherals_assignment_table_template}}
<section begin=stm32mp15 />
  | rowspan="14" | Core/Timers
  | rowspan="14" | Core/Timers
  | rowspan="14" | [[TIM internal peripheral|TIM]]
  | rowspan="14" | [[TIM internal peripheral|TIM]]
Line 122: Line 226:
  | <span title="assignable peripheral" style="font-size:21px">☐</span>
  | <span title="assignable peripheral" style="font-size:21px">☐</span>
  | <span title="assignable peripheral" style="font-size:21px">☐</span>
  | <span title="assignable peripheral" style="font-size:21px">☐</span>
  | Assignment (single choice)
  | Assignment (single choice)<br>TIM12 or TIM15 can be used for HSI/CSI calibration<ref name="calib">[[How to activate HSI and CSI oscillators calibration]]</ref>
  |-
  |-
  | TIM13 (APB1 group)
  | TIM13 (APB1 group)
Line 140: Line 244:
  | <span title="assignable peripheral" style="font-size:21px">☐</span>
  | <span title="assignable peripheral" style="font-size:21px">☐</span>
  | <span title="assignable peripheral" style="font-size:21px">☐</span>
  | <span title="assignable peripheral" style="font-size:21px">☐</span>
  | Assignment (single choice)
  | Assignment (single choice)<br>TIM12 or TIM15 can be used for HSI/CSI calibration<ref name="calib"/>
  |-
  |-
  | TIM16 (APB2 group)
  | TIM16 (APB2 group)
Line 154: Line 258:
  | Assignment (single choice)
  | Assignment (single choice)
  |-
  |-
</onlyinclude>
<section end=stm32mp15 />
  |}
  |}


Line 163: Line 267:
==References==
==References==
<references/>
<references/>
<noinclude>
[[Category:Timers peripherals]]
{{ArticleBasedOnModel| Internal peripheral article model}}
{{PublicationRequestId | 7895 | 2018-07-03 | AlainF}}
</noinclude>

Latest revision as of 15:37, 1 February 2022↑

Applicable for STM32MP13x lines, STM32MP15x lines

1. Article purpose↑

The purpose of this article is to

  • briefly introduce the TIM peripheral and its main features
  • indicate the level of security supported by this hardware block
  • explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
  • explain how to configure the TIM peripheral

2. Peripheral overview↑

The TIM peripheral is a multi-channel timer unit, available in various configurations, depending on the instance used. There are basically following categories: advanced-control timers, general-purpose timers and basic timers.

The TIM can provide: PWM with complementary output and dead-time insertion, break detection, input capture[1], quadrature encoder[2] interface (typically used for rotary encoders), trigger source for other internal peripherals like: ADC[3], DFSDM[4]. The full list can be found in Peripherals Interconnect matrix in the reference manual.

2.1. Features↑

The TIM peripheral is available in different configurations, depending on the selected instance :

  • TIM1 and TIM8 are advanced-control timers, with 6 independent channels.
  • TIM2, TIM3, TIM4 and TIM5 are general-purpose timers, with 4 independent channels.
  • TIM12, TIM13 and TIM14 are general-purpose timers, with 2 (TIM12) or 1 (TIM13 and TIM14) independent channels.
  • TIM15, TIM16 and TIM17 are also general-purpose timers, with 2 (TIM15) or 1 (TIM16 and TIM17) independent channels. Compare to TIM12, TIM13 and TIM14, this configuration brings some features that are very useful for motor control (like break function, DMA burst mode control, complementary output with dead-time insertion, ...)
  • TIM6 and TIM7 are basic timers

Refer to STM32MP13 reference manuals or STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to know which features are really implemented.


2.2. Security support↑


2.2.1. On STM32MP13x lines More info.png↑

There are 14 instances of TIM:

  • TIM instances 1, 2, 3, 4, 5, 6, 7 and 8 are non-secure peripheral
  • TIM instances 12, 13, 14, 15, 16 and 17 are secure (under ETZPC control)
2.2.2. On STM32MP15x lines More info.png↑

The 14 instances of TIM are non-secure peripherals.

3. Peripheral usage and associated software↑

3.1. Boot time↑

The TIM is not used at boot time.

3.2. Runtime↑

3.2.1. Overview↑

3.2.1.1. On STM32MP13x lines More info.png↑

TIM12 and/or TIM15 can be allocated to:

  • the Arm® Cortex®-A7 secure core to be controlled in the secure monitor (OP-TEE), to perform HSI and CSI calibrations[5] in RCC.

TIM13, TIM14, TIM16 and TIM17 can also be allocated to the Arm® Cortex®-A7 secure context, but there is no support for them in OP-TEE yet.
All TIM instances can be allocated to:

  • the Arm® Cortex®-A7 non-secure to be controlled in Linux® by the PWM, the IIO, and/or the Counter frameworks.
Info white.png Information
RCC[6] owns one prescaler per TIM group corresponding to APB1, APB2 and APB6 buses: TIMG1PRE, TIMG2PRE and TIMG3PRE, respectively. TIMG3PRE is securable in RCC. The allocation to Cortex-A7 contexts should ideally be done on a per group basis to get independent clocking setup on each side, this is why the TIM instances groups are shown in the summary table below (#Peripheral assignment)
3.2.1.2. On STM32MP15x lines More info.png↑

TIM12 and/or TIM15 can be allocated to:

  • the Arm® Cortex®-A7 secure core to be controlled in the secure monitor (TF-A or OP-TEE), to perform HSI and CSI calibrations[5] in RCC.

All TIM instances can be allocated to:

  • the Arm® Cortex®-A7 non-secure to be controlled in Linux® by the PWM, the IIO, and/or the Counter frameworks.

or

  • the Arm® Cortex®-M4 to be controlled in STM32Cube MPU Package by TIM HAL driver
Info white.png Information
RCC[6] owns one prescaler per TIM group corresponding to APB1 and APB2 buses: TIMG1PRE and TIMG2PRE, respectively. The allocation to Cortex-A7 or the Cortex-M4 should ideally be done on a per group basis to get independent clocking setup on each side, this is why the TIM instances groups are shown in the summary table below (#Peripheral assignment)

3.2.2. Software frameworks↑

3.2.2.1. On STM32MP13x lines More info.png↑
Domain Peripheral Software components Comment
OP-TEE Linux
Core/Timers TIM OP-TEE TIM driver PWM framework
IIO framework,
Counter framework
3.2.2.2. On STM32MP15x lines More info.png↑
Domain Peripheral Software components Comment
OP-TEE Linux STM32Cube
Core/Timers TIM TF-A TIM driver
OP-TEE TIM driver 		PWM framework
IIO framework,
Counter framework 		STM32Cube TIM driver

3.2.3. Peripheral configuration↑

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be performed via the STM32CubeMX tool for all internal peripherals. It can then be manually completed (especially for external peripherals) according to the information given in the corresponding software framework article.

For Linux kernel configuration, please refer to TIM device tree configuration and TIM Linux driver articles.

3.2.4. Peripheral assignment↑

3.2.4.1. On STM32MP13x lines More info.png↑

Click on the right to expand the legend...

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE) 		Cortex-A7
non-secure
(Linux)
Core/Timers TIM TIM1 (APB2 group) ☐
TIM2 (APB1 group) ☐
TIM3 (APB1 group) ☐
TIM4 (APB1 group) ☐
TIM5 (APB1 group) ☐
TIM6 (APB1 group) ☐
TIM7 (APB1 group) ☐
TIM8 (APB2 group) ☐
TIM12 (APB6 group) ☐ ☐ Assignment (single choice)
TIM12 or TIM15 can be used for HSI/CSI calibration[5]
TIM13 (APB6 group) ⬚ ☐ Assignment (single choice)
TIM14 (APB6 group) ⬚ ☐ Assignment (single choice)
TIM15 (APB6 group) ☐ ☐ Assignment (single choice)
TIM12 or TIM15 can be used for HSI/CSI calibration[5]
TIM16 (APB6 group) ⬚ ☐ Assignment (single choice)
TIM17 (APB6 group) ⬚ ☐ Assignment (single choice)
3.2.4.2. On STM32MP15x lines More info.png↑

Click on the right to expand the legend...

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE) 		Cortex-A7
non-secure
(Linux) 		Cortex-M4

(STM32Cube)
Core/Timers TIM TIM1 (APB2 group) ☐ ☐ Assignment (single choice)
TIM2 (APB1 group) ☐ ☐ Assignment (single choice)
TIM3 (APB1 group) ☐ ☐ Assignment (single choice)
TIM4 (APB1 group) ☐ ☐ Assignment (single choice)
TIM5 (APB1 group) ☐ ☐ Assignment (single choice)
TIM6 (APB1 group) ☐ ☐ Assignment (single choice)
TIM7 (APB1 group) ☐ ☐ Assignment (single choice)
TIM8 (APB2 group) ☐ ☐ Assignment (single choice)
TIM12 (APB1 group) ☐ ☐ ☐ Assignment (single choice)
TIM12 or TIM15 can be used for HSI/CSI calibration[5]
TIM13 (APB1 group) ☐ ☐ Assignment (single choice)
TIM14 (APB1 group) ☐ ☐ Assignment (single choice)
TIM15 (APB2 group) ☐ ☐ ☐ Assignment (single choice)
TIM12 or TIM15 can be used for HSI/CSI calibration[5]
TIM16 (APB2 group) ☐ ☐ Assignment (single choice)
TIM17 (APB2 group) ☐ ☐ Assignment (single choice)

4. How to go further↑

STM32 cross-series timer overview[7] application note.

5. References↑

  1. ↑ Input capture
  2. ↑ Quadrature encoder
  3. ↑ ADC internal peripheral
  4. ↑ DFSDM internal peripheral
  5. ↑ Jump up to: 5.0 5.1 5.2 5.3 5.4 5.5 How to activate HSI and CSI oscillators calibration
  6. ↑ Jump up to: 6.0 6.1 RCC internal peripheral
  7. ↑ STM32 cross-series timer overview application note

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