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<noinclude>{{ApplicableFor
|MPUs list=STM32MP13x, STM32MP15x
|MPUs checklist=STM32MP13x,STM32MP15x
}}</noinclude>
==Article purpose==
==Article purpose==
The purpose of this article is to
The purpose of this article is to
* briefly introduce the '''LPTIM''' peripheral and its main features
* briefly introduce the '''LPTIM''' peripheral and its main features
* indicate the level of security supported by this hardware block
* indicate the level of security supported by this hardware block
* explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
* explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
* explain how to configure the LPTIM peripheral
* explain how to configure the LPTIM peripheral


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===Features===
===Features===
Refer to [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to know which features are really implemented.
Refer to [[STM32MP13 resources#Reference manuals|STM32MP13 reference manuals]] or [[STM32MP15 resources#Reference manuals|STM32MP15 reference manuals]] for the complete list of features, and to the software components, introduced below, to know which features are really implemented.


The LPTIM peripheral is available in different configurations, depending on the selected instance :
The LPTIM peripheral is available in different configurations. Depending on the selected instance, it can act as
* LPTIM1 and LPTIM2 can act as PWM, quadrature encoder<ref name="quadrature_encoder">[https://en.wikipedia.org/wiki/Rotary_encoder#Incremental_rotary_encoder Quadrature encoder]</ref>, external event counter, trigger source for other internal peripherals like: ADC<ref name="adc_internal">[[ADC internal peripheral]]</ref>, DAC<ref name="dac_internal">[[DAC internal peripheral]]</ref>, DFSDM<ref name="dfsdm_internal">[[DFSDM internal peripheral]]</ref>.
PWM, quadrature encoder<ref name="quadrature_encoder">[https://en.wikipedia.org/wiki/Rotary_encoder#Incremental_rotary_encoder Quadrature encoder]</ref>,
* LPTIM3 can act as PWM, external event counter, trigger source for other internal peripherals like ADC<ref name="adc_internal"/>, DFSDM<ref name="dfsdm_internal"/>.
external event counter or trigger source for other internal peripherals, like ADC<ref name="adc_internal">[[ADC internal peripheral]]</ref>, DFSDM<ref name="dfsdm_internal">[[DFSDM internal peripheral]]</ref> and DAC<ref name="dac_internal">[[DAC internal peripheral]]</ref> (on {{MicroprocessorDevice | device=15}}).
* LPTIM4 and LPTIM5 can act as PWM.
 
{| class="st-table" style="width: 100%;"
|- style="background: {{STLightGrey}};"
! style="width:40%;  | LPTIM features
! style="width:20%;  | PWM
! style="width:20%;" | External event counter <br/>Trigger source
! style="width:20%;" | Quadrature encoder
|-
| LPTIM1, LPTIM2
| {{Y}}
| {{Y}}
| {{Y}}
|-
| LPTIM3
| {{Y}}
| {{Y}}
|
|-
| LPTIM4, LPTIM5
| {{Y}}
|
|
|-
|}
 
* On {{MicroprocessorDevice | device=13}}, LPTIM3 can be used for [[RCC internal peripheral|RCC]] HSE clock source monitoring


===Security support===
===Security support===
The LPTIM is a '''non-secure''' peripheral.
{{ReviewsComments | [[User:Olivier Moysan|Olivier Moysan]] ([[User talk:Olivier Moysan|talk]]) 15:39, 29 November 2021 (CET) - This section is redundant with Peripheral assignment section. So I suggest to remove it.}}
 
===== On {{MicroprocessorDevice | device=13}} =====
There are 5 instances of LPTIM:
* LPTIM instances 1, 4 and 5 are '''non-secure''' peripheral
* LPTIM instances 2 and  3 are '''secure''' (under [[ETZPC_internal_peripheral|ETZPC]] control)
===== On {{MicroprocessorDevice | device=15}} =====
The 5 LPTIM instances are a '''non-secure''' peripherals.


==Peripheral usage and associated software==
==Peripheral usage and associated software==
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===Runtime===
===Runtime===
====Overview====
====Overview====
===== On {{MicroprocessorDevice | device=13}} =====
LPTIM instances can be allocated to:
LPTIM instances can be allocated to:
*the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure to be used under Linux<sup>&reg;</sup> with [[PWM overview|PWM]] and/or [[IIO overview|IIO]] frameworks.
*the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 secure to be used under OP-TEE
or
*the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure to be used under Linux<sup>&reg;</sup> with [[PWM overview|PWM]],  [[IIO overview|IIO]], ''Counter'' or/and ''Clock events'' frameworks
===== On {{MicroprocessorDevice | device=15}} =====
LPTIM instances can be allocated to:
*the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-A7 non-secure to be used under Linux<sup>&reg;</sup> with [[PWM overview|PWM]],  [[IIO overview|IIO]], ''Counter'' or/and ''Clock events'' frameworks,
or
or
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 to be used with STM32Cube MPU Package with [[STM32CubeMP1 architecture|LPTIM HAL driver]]
* the Arm<sup>&reg;</sup> Cortex<sup>&reg;</sup>-M4 to be used with STM32Cube MPU Package with [[STM32CubeMP1 architecture|LPTIM HAL driver]]


====Software frameworks====
====Software frameworks====
{{:Internal_peripherals_software_table_template}}
===== On {{MicroprocessorDevice | device=13}} =====
{{:STM32MP13_internal_peripherals_software_table_template}}
| Core/Timers
| [[LPTIM internal peripheral|LPTIM]]
| [[OP-TEE overview|OP-TEE]]
| [[PWM overview|PWM framework]],<br>[[IIO overview|IIO framework]],<br>''Counter'' framework,<br>''Clock events'' framework
|
|-
|}
===== On {{MicroprocessorDevice | device=15}} =====
{{:STM32MP15_internal_peripherals_software_table_template}}
  | Core/Timers
  | Core/Timers
  | [[LPTIM internal peripheral|LPTIM]]
  | [[LPTIM internal peripheral|LPTIM]]
  |  
  |  
  | [[PWM overview|Linux PWM framework]]<br>[[IIO overview|Linux IIO framework]]
  | [[PWM overview|PWM framework]],<br>[[IIO overview|IIO framework]],<br>''Counter'' framework,<br>''Clock events'' framework
  | [[STM32CubeMP1 architecture|STM32Cube LPTIM driver]]
  | [[STM32CubeMP1 architecture|STM32Cube LPTIM driver]]
  |
  |
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====Peripheral assignment====
====Peripheral assignment====
{{:Internal_peripherals_assignment_table_template}}
===== On {{MicroprocessorDevice | device=13}} =====
<onlyinclude>
{{:STM32MP13_internal_peripherals_assignment_table_template}}
<section begin=stm32mp13 />
| rowspan="5" | Core/Timers
| rowspan="5" | [[LPTIM internal peripheral|LPTIM]]
| LPTIM1
|
| <span title="assignable peripheral" style="font-size:21px">☐</span>
|
|-
| LPTIM2
| <span title="assignable peripheral but not supported" style="font-size:21px">⬚</span>
| <span title="assignable peripheral" style="font-size:21px">☐</span>
| Assignment (single choice)
|-
| LPTIM3
| <span title="assignable peripheral" style="font-size:21px">☐</span>
| <span title="assignable peripheral" style="font-size:21px">☐</span>
| Assignment (single choice)<br>LPTIM3 can be used for HSE monitoring
|-
| LPTIM4
|
| <span title="assignable peripheral" style="font-size:21px">☐</span>
|
|-
| LPTIM5
|
| <span title="assignable peripheral" style="font-size:21px">☐</span>
| Assignment (single choice)
|-
<section end=stm32mp13 />
|}
===== On {{MicroprocessorDevice | device=15}} =====
{{:STM32MP15_internal_peripherals_assignment_table_template}}
<section begin=stm32mp15 />
  | rowspan="5" | Core/Timers
  | rowspan="5" | Core/Timers
  | rowspan="5" | [[LPTIM internal peripheral|LPTIM]]
  | rowspan="5" | [[LPTIM internal peripheral|LPTIM]]
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  | Assignment (single choice)
  | Assignment (single choice)
  |-
  |-
</onlyinclude>
<section end=stm32mp15 />
  |}
  |}


Latest revision as of 15:36, 1 February 2022↑

Applicable for STM32MP13x lines, STM32MP15x lines

1. Article purpose↑

The purpose of this article is to

  • briefly introduce the LPTIM peripheral and its main features
  • indicate the level of security supported by this hardware block
  • explain how each instance can be allocated to the runtime contexts and linked to the corresponding software components
  • explain how to configure the LPTIM peripheral

2. Peripheral overview↑

The LPTIM peripheral is a single channel low-power timer unit, that can continue to run even during low power modes when it selects a clock source that remains active in RCC.

2.1. Features↑

Refer to STM32MP13 reference manuals or STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to know which features are really implemented.

The LPTIM peripheral is available in different configurations. Depending on the selected instance, it can act as PWM, quadrature encoder[1], external event counter or trigger source for other internal peripherals, like ADC[2], DFSDM[3] and DAC[4] (on STM32MP15x lines More info.png).

LPTIM features PWM External event counter
Trigger source 		Quadrature encoder
LPTIM1, LPTIM2 Yes Yes Yes
LPTIM3 Yes Yes
LPTIM4, LPTIM5 Yes
  • On STM32MP13x lines More info.png, LPTIM3 can be used for RCC HSE clock source monitoring

2.2. Security support↑


2.2.1. On STM32MP13x lines More info.png↑

There are 5 instances of LPTIM:

  • LPTIM instances 1, 4 and 5 are non-secure peripheral
  • LPTIM instances 2 and 3 are secure (under ETZPC control)
2.2.2. On STM32MP15x lines More info.png↑

The 5 LPTIM instances are a non-secure peripherals.

3. Peripheral usage and associated software↑

3.1. Boot time↑

The LPTIM is not used at boot time.

3.2. Runtime↑

3.2.1. Overview↑

3.2.1.1. On STM32MP13x lines More info.png↑

LPTIM instances can be allocated to:

  • the Arm® Cortex®-A7 secure to be used under OP-TEE

or

  • the Arm® Cortex®-A7 non-secure to be used under Linux® with PWM, IIO, Counter or/and Clock events frameworks
3.2.1.2. On STM32MP15x lines More info.png↑

LPTIM instances can be allocated to:

  • the Arm® Cortex®-A7 non-secure to be used under Linux® with PWM, IIO, Counter or/and Clock events frameworks,

or

  • the Arm® Cortex®-M4 to be used with STM32Cube MPU Package with LPTIM HAL driver

3.2.2. Software frameworks↑

3.2.2.1. On STM32MP13x lines More info.png↑
Domain Peripheral Software components Comment
OP-TEE Linux
Core/Timers LPTIM OP-TEE PWM framework,
IIO framework,
Counter framework,
Clock events framework
3.2.2.2. On STM32MP15x lines More info.png↑
Domain Peripheral Software components Comment
OP-TEE Linux STM32Cube
Core/Timers LPTIM PWM framework,
IIO framework,
Counter framework,
Clock events framework 		STM32Cube LPTIM driver

3.2.3. Peripheral configuration↑

The configuration is applied by the firmware running in the context to which the peripheral is assigned. The configuration by itself can be performed via STM32CubeMX tool for all internal peripherals. It can then be manually completed (especially for external peripherals) according to the information given in the corresponding software framework article.

For Linux kernel configuration, please refer to LPTIM device tree configuration and STM32 LPTIM Linux driver articles.

3.2.4. Peripheral assignment↑

3.2.4.1. On STM32MP13x lines More info.png↑

Click on the right to expand the legend...

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE) 		Cortex-A7
non-secure
(Linux)
Core/Timers LPTIM LPTIM1 ☐
LPTIM2 ⬚ ☐ Assignment (single choice)
LPTIM3 ☐ ☐ Assignment (single choice)
LPTIM3 can be used for HSE monitoring
LPTIM4 ☐
LPTIM5 ☐ Assignment (single choice)
3.2.4.2. On STM32MP15x lines More info.png↑

Click on the right to expand the legend...

Domain Peripheral Runtime allocation Comment
Instance Cortex-A7
secure
(OP-TEE) 		Cortex-A7
non-secure
(Linux) 		Cortex-M4

(STM32Cube)
Core/Timers LPTIM LPTIM1 ☐ ☐ Assignment (single choice)
LPTIM2 ☐ ☐ Assignment (single choice)
LPTIM3 ☐ ☐ Assignment (single choice)
LPTIM4 ☐ ☐ Assignment (single choice)
LPTIM5 ☐ ☐ Assignment (single choice)

4. References↑

  1. ↑ Quadrature encoder
  2. ↑ ADC internal peripheral
  3. ↑ DFSDM internal peripheral
  4. ↑ DAC internal peripheral



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