DDRCTRL and DDRPHYC internal peripherals

1 Article purpose

The purpose of this article is to:

• briefly introduce the DDRCTRL and DDRPHYC peripherals and their main features
• indicate the level of security supported by those hardware blocks
• explain how they can be allocated to the runtime contexts and linked to the corresponding software components
• explain, when necessary, how to configure the DDRCTRL and DDRPHYC peripherals.

2 Peripheral overview

DDRCTRL and DDRPHYC peripherals are used to configure the physical interface to the external DDR memory.

Notice that it is possible to perform DDR bandwidth measurement thanks to the DDRPERFM internal peripheral.

2.1 Features

Refer to STM32MP13 reference manuals or STM32MP15 reference manuals for the complete features list, and to the software components, introduced below, to see which features are actually implemented.

2.2 Security support

DDRCTRL and DDRPHYC are secure (under ETZPC control).

Access to the DDR memory can be filtered via the TZC controller.

3 Peripheral usage and associated software

3.1 Boot time

DDRCTRL and DDRPHYC are kept secure and used by the FSBL to initialize the access to the DDR where it loads the SSBL (U-Boot) for execution.
STMicroelectronics wishes to make the DDR memory configuration as easy as possible, for this reason a dedicated application note has been published and a DDR tuning function is available in STM32CubeMX tool in order to generate the device tree configuration that is given to the FSBL to perform this initialization.

3.2 Runtime

3.2.1 Overview

DDRCTRL and DDRPHYC are accessed at runtime by the secure monitor (from the FSBL or OP-TEE) to put the DDR in self-refresh state before going into Stop or Standby low power mode.
On Standby exit, the ROM code loads the FSBL that again configures the DDRCTRL and DDRPHYC before proceeding with the wake-up procedure.
The TZC controller configures DDR memory access.

3.2.2 Software frameworks

3.2.2.1 On STM32MP13x lines 

Domain	Peripheral	Software components		Comment
		OP-TEE	Linux
Core/RAM	DDR via DDRCTRL	DDR OP-TEE driver

3.2.2.2 On STM32MP15x lines 

Internal peripherals software table template

| Core/RAM
| DDR via DDRCTRL
| DDR OP-TEE driver
| 
| 
|
|-
|}

3.2.3 Peripheral configuration

The DDRCTRL and DDRPHYC device tree configuration is generated via STM32CubeMX tool, according to the DDR characteristics (type, size, frequency, speed grade). This configuration is applied during boot time by the FSBL (see Boot chain overview).

3.2.4 Peripheral assignment

3.2.4.1 On STM32MP13x lines 

Click on the right to expand the legend...

Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:

• ☐ means that the peripheral can be assigned (☑) to the given runtime context.
• ⬚ means that the peripheral can be assigned to the given runtime context, but this configuration is not supported in STM32 MPU Embedded Software distribution.
• ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.

Refer to How to assign an internal peripheral to an execution context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP13 reference manuals.

Domain	Peripheral	Runtime allocation			Comment
		Instance	Cortex-A7 secure (OP-TEE)	Cortex-A7 non-secure (Linux)
Core/RAM	DDR via DDRCTRL	DDR	✓	✓

3.2.4.2 On STM32MP15x lines 

Internal peripherals assignment table template

| rowspan="1" | Core/RAM
| rowspan="1" | DDR via DDRCTRL
| DDR
| ✓
| ✓
|
|
|-

|}