- Last edited 2 years ago ago
ETM internal peripheral
Contents
1 Article purpose[edit]
The purpose of this article is to:
- Briefly introduce the ETM peripheral and its main features
- Indicate the level of security supported by this hardware block
- Explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
- Explain, when necessary, how to configure the ETM peripheral.
2 Peripheral overview[edit]
The ETM peripheral is used to log the Cortex®-A7 execution trace into the embedded trace FIFO (ETF). Once in the ETF buffer, the trace can directly be dumped from the Cortex®-A7 or to the trace port interface unit (TPIU), connected to an external probe able to decode it.
This peripheral has two instances, one for each Cortex®-A7 core.
2.1 Features[edit]
Refer to the STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are really implemented.
2.2 Security support[edit]
The ETM is a non secure peripheral.
3 Peripheral usage and associated software[edit]
3.1 Boot time[edit]
The ETM can be used to debug the boot sequence using external probe.
3.2 Runtime[edit]
3.2.1 Overview[edit]
The ETM can be used to debug the run time application using external probe.
3.2.2 Software frameworks[edit]
There is no software dedicated to the ETM internal peripheral delivered with STM32MPU ecosystem. Nevertheless, the ETM trace can be captured using an external probe.
3.2.3 Peripheral configuration[edit]
Configuration of the ETM is done via JTAG scripts. Those scripts must be built by user thanks to STM32MP15 reference manuals .
3.2.4 Peripheral assignment[edit]
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ☐ means that the peripheral can be assigned (☑) to the given runtime context.
- ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.
Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment | |||
|---|---|---|---|---|---|---|
| Instance | Cortex-A7 secure (OP-TEE) |
Cortex-A7 non-secure (Linux) |
Cortex-M4 (STM32Cube) | |||
| Trace & Debug | ETM | ETM0 | ✓ | ✓ | ||
| ETM1 | ✓ | ✓ | ||||