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== Article purpose == | == Article purpose == | ||
This article explains how to configure the [[QUADSPI internal peripheral|'''QUADSPI''' internal peripheral]] when it is assigned to the Linux<sup>®</sup> OS. In that case, it is controlled by the [[MTD overview|MTD framework]]. | This article explains how to configure the [[QUADSPI internal peripheral|'''QUADSPI''' internal peripheral]] when it is assigned to the Linux<sup>®</sup> OS. In that case, it is controlled by the [[MTD overview|MTD framework]]. | ||
The configuration is performed using the [[Device tree|device tree]] mechanism that provides a hardware description of the QUADSPI peripheral, used by the STM32 QUADSPI Linux driver and by the MTD framework. | The configuration is performed using the [[Device tree|device tree]] mechanism that provides a hardware description of the QUADSPI peripheral, used by the STM32 QUADSPI Linux driver and by the MTD framework. | ||
If the peripheral is assigned to another execution context, refer to [[How to assign an internal peripheral to a runtime context]] article for guidelines on peripheral assignment and configuration. | |||
== DT bindings documentation == | == DT bindings documentation == | ||
| Line 17: | Line 10: | ||
The QUADSPI device tree bindings are composed by: | The QUADSPI device tree bindings are composed by: | ||
* generic | * generic SPI-NOR / SPI-NAND Flash memory bindings <ref name="spi_busses_bindings">{{CodeSource | Linux kernel | Documentation/devicetree/bindings/spi/spi-bus.txt}}</ref>. | ||
* QUADSPI driver bindings <ref> {{CodeSource | Linux kernel | Documentation/devicetree/bindings/spi/spi-stm32-qspi.txt}} </ref>. | * QUADSPI driver bindings <ref> {{CodeSource | Linux kernel | Documentation/devicetree/bindings/spi/spi-stm32-qspi.txt}} </ref>. | ||
In next chapters, SPI-NAND bindings are only compatible with {{EcosystemRelease | revision=1.1.0 | range=and after}}. | |||
== DT configuration == | == DT configuration == | ||
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reg-names = "qspi", "qspi_mm"; | reg-names = "qspi", "qspi_mm"; | ||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; {{highlight|--> The interrupt number used}} | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; {{highlight|--> The interrupt number used}} | ||
dmas = <&mdma1 22 0x10 | dmas = <&mdma1 22 0x10 0x100002 0x0 0x0 0x0>, {{highlight|--> DMA specifiers <ref>{{CodeSource | Linux kernel | Documentation/devicetree/bindings/dma/stm32-mdma.txt}}</ref>}} | ||
<&mdma1 22 0x10 | <&mdma1 22 0x10 0x100008 0x0 0x0 0x0>; | ||
dma-names = "tx", "rx"; | dma-names = "tx", "rx"; | ||
clocks = <&rcc QSPI_K>; | clocks = <&rcc QSPI_K>; | ||
| Line 46: | Line 41: | ||
=== DT configuration (board level) === | === DT configuration (board level) === | ||
The QUADSPI peripheral may connect a maximum of 2 | The QUADSPI peripheral may connect a maximum of 2 SPI-NOR Flash memories. | ||
SPI-NOR Flash memory nodes <ref name="spi_busses_bindings"/> must be children of the QUADSPI peripheral node. | |||
&qspi { {{highlight|Comments}} | &qspi { {{highlight|Comments}} | ||
| Line 70: | Line 65: | ||
=== DT configuration example === | === DT configuration example === | ||
The below example shows how to configure the QUADSPI peripheral when | The below example shows how to configure the QUADSPI peripheral when 1 SPI-NAND Flash and 1 SPI-NOR Flash memories are connected. | ||
&qspi { | &qspi { | ||
pinctrl-names = "default", "sleep"; | pinctrl-names = "default", "sleep"; | ||
pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; | pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; | ||
pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; | pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; | ||
reg = <0x58003000 0x1000>, | reg = <0x58003000 0x1000>, | ||
<0x70000000 0x4000000>; | <0x70000000 0x4000000>; | ||
#address-cells = <1>; | #address-cells = <1>; | ||
#size-cells = <0>; | #size-cells = <0>; | ||
status = "okay";<br> | status = "okay";<br> | ||
flash0: mx66l51235l@0 { | flash0: mx66l51235l@0 { | ||
compatible = "jdec,spi-nor"; | compatible = "jdec,spi-nor"; | ||
reg = <0>; | reg = <0>; | ||
| Line 89: | Line 84: | ||
#size-cells = <1>; | #size-cells = <1>; | ||
};<br> | };<br> | ||
flash1: | flash1: mt29f2g01abagd@1 { | ||
compatible = " | compatible = "spi-nand"; | ||
reg = <1>; | reg = <1>; | ||
spi-rx-bus-width = <4>; | spi-rx-bus-width = <4>; | ||
spi-max-frequency = < | spi-tx-bus-width = <4>; | ||
spi-max-frequency = <133000000>; | |||
#address-cells = <1>; | #address-cells = <1>; | ||
#size-cells = <1>; | #size-cells = <1>; | ||
| Line 107: | Line 103: | ||
<references /> | <references /> | ||
<noinclude> | |||
{{ArticleBasedOnModel | Peripheral or framework device tree configuration model}} | |||
{{PublicationRequestId | 8899 |2018-10-10 | AlainF}} | |||
[[Category:Device tree configuration]] | |||
[[Category:Mass storage]] | |||
</noinclude> | |||
Latest revision as of 16:49, 6 February 2020
1. Article purpose
This article explains how to configure the QUADSPI internal peripheral when it is assigned to the Linux® OS. In that case, it is controlled by the MTD framework.
The configuration is performed using the device tree mechanism that provides a hardware description of the QUADSPI peripheral, used by the STM32 QUADSPI Linux driver and by the MTD framework.
If the peripheral is assigned to another execution context, refer to How to assign an internal peripheral to a runtime context article for guidelines on peripheral assignment and configuration.
2. DT bindings documentation
The QUADSPI device tree bindings are composed by:
- generic SPI-NOR / SPI-NAND Flash memory bindings [1].
- QUADSPI driver bindings [2].
In next chapters, SPI-NAND bindings are only compatible with ecosystem release ≥ v1.1.0 
.
3. DT configuration
This hardware description is a combination of the STM32 microprocessor device tree files (.dtsi extension) and board device tree files (.dts extension). See the Device tree for an explanation of the device tree file split.
STM32CubeMX can be used to generate the board device tree. Refer to How to configure the DT using STM32CubeMX for more details.
3.1. DT configuration (STM32 level)
The QUADSPI peripheral node is located in stm32mp157c.dtsi[3] file.
qspi: spi@58003000 { Template:Highlight compatible = "st,stm32f469-qspi"; reg = <0x58003000 0x1000>, Template:Highlight <0x70000000 0x10000000>; Template:Highlight reg-names = "qspi", "qspi_mm"; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; Template:Highlight dmas = <&mdma1 22 0x10 0x100002 0x0 0x0 0x0>, Template:Highlight <&mdma1 22 0x10 0x100008 0x0 0x0 0x0>; dma-names = "tx", "rx"; clocks = <&rcc QSPI_K>; resets = <&rcc QSPI_R>; status = "disabled"; };
3.2. DT configuration (board level)
The QUADSPI peripheral may connect a maximum of 2 SPI-NOR Flash memories.
SPI-NOR Flash memory nodes [1] must be children of the QUADSPI peripheral node.
&qspi { Template:Highlight pinctrl-names = "default", "sleep"; Template:Highlight pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; Template:Highlight #address-cells = <1>; #size-cells = <0>; status = "okay"; Template:Highlight
flash0: mx66l51235l@0 { compatible = "jdec,spi-nor"; reg = <0>; Template:Highlight spi-rx-bus-width = <4>; Template:Highlight spi-max-frequency = <108000000>; Template:Highlight #address-cells = <1>; #size-cells = <1>; }; };
3.3. DT configuration example
The below example shows how to configure the QUADSPI peripheral when 1 SPI-NAND Flash and 1 SPI-NOR Flash memories are connected.
&qspi { pinctrl-names = "default", "sleep"; pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; status = "okay";
flash0: mx66l51235l@0 { compatible = "jdec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; #address-cells = <1>; #size-cells = <1>; };
flash1: mt29f2g01abagd@1 { compatible = "spi-nand"; reg = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; spi-max-frequency = <133000000>; #address-cells = <1>; #size-cells = <1>; }; };
4. How to configure the DT using STM32CubeMX
The STM32CubeMX tool can be used to configure the STM32MPU device and get the corresponding platform configuration device tree files.
The STM32CubeMX may not support all the properties described in the above DT bindings documentation paragraph. If so, the tool inserts user sections in the generated device tree. These sections can then be edited to add some properties and they are preserved from one generation to another. Refer to STM32CubeMX user manual for further information.
5. References
Please refer to the following links for full description: