deleted>Frq08988 mNo edit summary |
Registered User (add some information about OTP access conditions) |
||
| (6 intermediate revisions by 3 users not shown) | |||
| Line 1: | Line 1: | ||
==Article purpose== | ==Article purpose== | ||
The purpose of this article is to | The purpose of this article is to | ||
| Line 30: | Line 22: | ||
====Overview==== | ====Overview==== | ||
The BSEC instance is a system peripheral and is controlled by the Arm<sup>®</sup> Cortex<sup>®</sup>-A7 secure. | The BSEC instance is a system peripheral and is controlled by the Arm<sup>®</sup> Cortex<sup>®</sup>-A7 secure: | ||
{{Info| | |||
:* BSEC lower OTP access can be made available to the Arm<sup>®</sup> Cortex<sup>®</sup>-A7 non-secure. | |||
:* Upper OTP access can be managed as exceptions (in Trusted Boot Chain only, using [[TF-A overview|TF-A]]), via "secure monitor calls", managed by [[TF-A_overview|TF-A]] or by [[OP-TEE_overview|OP-TEE]]. Please refer to [[BSEC device tree configuration]] for more details.}} | |||
====Software frameworks==== | ====Software frameworks==== | ||
| Line 44: | Line 40: | ||
====Peripheral configuration==== | ====Peripheral configuration==== | ||
The configuration is applied by the firmware running in a secure context | The configuration is based on [[Device tree]], please refer to [[BSEC device tree configuration]] article.<br/> | ||
It can be applied by the firmware running in a secure context, done in [[TF-A_overview|TF-A]] or in [[OP-TEE_overview|OP-TEE]].<br/> | |||
It can also be configured by Linux<sup>®</sup> kernel, please refer to [[NVMEM overview]] article. | |||
====Peripheral assignment==== | ====Peripheral assignment==== | ||
| Line 66: | Line 62: | ||
==References== | ==References== | ||
<references/> | <references/> | ||
<noinclude> | |||
[[Category:Persistent storage peripherals]] | |||
{{ArticleBasedOnModel| Contributors:Internal_peripheral_article_model}} | |||
{{PublicationRequestId | 8892 (PhilipS) | 2018-10-17}} | |||
</noinclude> | |||
Latest revision as of 09:57, 24 September 2019
1. Article purpose
The purpose of this article is to
- briefly introduce the BSEC peripheral and its main features
- indicate the level of security supported by this hardware block
- explain how each instance can be allocated to the three runtime contexts and linked to the corresponding software components
- explain, when necessary, how to configure the BSEC peripheral.
2. Peripheral overview
The BSEC peripheral is used to control an OTP (one time programmable) fuse box, used for on-chip non-volatile storage for device configuration and security parameters.
2.1. Features
Refer to STM32MP15 reference manuals for the complete list of features, and to the software components, introduced below, to see which features are implemented.
2.2. Security support
The BSEC is a secure peripheral.
3. Peripheral usage and associated software
3.1. Boot time
The BSEC is configured at boot time to set up platform security.
3.2. Runtime
3.2.1. Overview
The BSEC instance is a system peripheral and is controlled by the Arm® Cortex®-A7 secure:
3.2.2. Software frameworks
| Domain | Peripheral | Software frameworks | Comment | ||
| Cortex-A7 S (OP-TEE) |
Cortex-A7 NS (Linux) |
Cortex-M4 (STM32Cube) | |||
| Security | BSEC | OP-TEE BSEC driver | Linux NVMEM framework | ||
3.2.3. Peripheral configuration
The configuration is based on Device tree, please refer to BSEC device tree configuration article.
It can be applied by the firmware running in a secure context, done in TF-A or in OP-TEE.
It can also be configured by Linux® kernel, please refer to NVMEM overview article.
3.2.4. Peripheral assignment
Check boxes illustrate the possible peripheral allocations supported by STM32 MPU Embedded Software:
- ☐ means that the peripheral can be assigned (☑) to the given runtime context.
- ✓ is used for system peripherals that cannot be unchecked because they are statically connected in the device.
Refer to How to assign an internal peripheral to a runtime context for more information on how to assign peripherals manually or via STM32CubeMX.
The present chapter describes STMicroelectronics recommendations or choice of implementation. Additional possiblities might be described in STM32MP15 reference manuals.
| Domain | Peripheral | Runtime allocation | Comment | |||
| Instance | Cortex-A7 S (OP-TEE) |
Cortex-A7 NS (Linux) |
Cortex-M4 (STM32Cube) | |||
| Security | BSEC | BSEC | ✓ | ✓ | ||
4. How to go further
5. References